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publication release date: january 26, 2015 - 1 - revision j 3v 16m - bit serial flash memory with dual and quad spi
- 2 - table of contents 1. general description ................................ ................................ ................................ ............... 5 2. features ................................ ................................ ................................ ................................ ....... 5 3. package types and pi n configurations ................................ ................................ .......... 6 3.1 pin configuration soic 150 / 208 - mil ................................ ................................ .................. 6 3.2 pad configuration wson 6x5 - mm / uson 4x3 - mm / uson 4x4 - mm .............................. 6 3.3 pin configuration pdip 300 - mil ................................ ................................ ............................ 7 3.4 pin description soic 150/208 - mil, wson 6x5 - mm / uson 4x3 - mm / pdip 300 - mil ........ 7 3.5 pin configuration soic 300 - mil ................................ ................................ ........................... 8 3.6 pin description soic 300 - mil ................................ ................................ ............................... 8 3.7 ball configuration tfbga 8x6mm ................................ ................................ ....................... 9 3.8 ball description tfbga 8x6 - mm ................................ ................................ ......................... 9 4. pin descriptions ................................ ................................ ................................ ...................... 10 4.1 chip select (/cs) ................................ ................................ ................................ ................ 10 4.2 serial data input, output and ios (d i, do and io0, io1, io2, io3) ................................ .. 10 4.3 write protect (/wp) ................................ ................................ ................................ ............. 10 4.4 hold (/hold) ................................ ................................ ................................ ................... 10 4.5 serial clock (clk) ................................ ................................ ................................ .............. 10 5. block diagram ................................ ................................ ................................ .......................... 11 6. functional descripti on ................................ ................................ ................................ ....... 12 6.1 spi operations ................................ ................................ ................................ ............. 12 6.1.1 standard spi instructions ................................ ................................ ................................ ..... 12 6.1.2 dual spi instructions ................................ ................................ ................................ ............ 12 6.1.3 quad spi instructions ................................ ................................ ................................ ........... 12 6.1.4 hold function ................................ ................................ ................................ ........................ 12 6.2 write protection ................................ ................................ ................................ ....... 13 6.2.1 write protect features ................................ ................................ ................................ .......... 13 7. status registers and instructions ................................ ................................ ............... 14 7.1 status registers ................................ ................................ ................................ ........ 14 7.1.1 busy status (busy) ................................ ................................ ................................ ............ 14 7.1.2 write enable latch status (wel) ................................ ................................ ......................... 14 7.1.3 block protect bits (bp2, bp1, bp0) ................................ ................................ ...................... 14 7.1.4 top/bottom block protect bit (tb) ................................ ................................ ........................ 14 7.1 .5 sector/block protect bit (sec) ................................ ................................ ............................. 14 7.1.6 complement protect bit (cmp) ................................ ................................ ............................. 14 7.1.7 status register protect bits (srp 1, srp0 ) ................................ ................................ .......... 15 7.1.8 erase/program suspend status (sus) ................................ ................................ ................. 15 7.1.9 security register lock bits (lb3, lb2, lb1) ................................ ................................ ......... 15 7.1.10 quad enable bit ( qe ) ................................ ................................ ................................ ......... 15
publication release date: january 26, 2015 - 3 - revision j 7.1.11 status register memory protection (cmp = 0) ................................ ................................ ... 17 7.1.12 statu s register memory protection (cmp = 1) ................................ ................................ ... 18 7.2 instructions ................................ ................................ ................................ ................. 19 7.2.1 manufacturer and device identification ................................ ................................ ................. 19 7.2.2 instruction set table 1 (erase, program instructions) ( 1 ) ................................ ....................... 20 7.2.3 instruction set table 2 (read instructions) ................................ ................................ ........... 21 7.2.4 instruction set table 3 (id, security instructions) ................................ ................................ . 22 7.2.5 write enable (06h) ................................ ................................ ................................ ................ 23 7. 2.6 write enable for volatile status register (50h) ................................ ................................ ..... 23 7.2.7 write disable (04h) ................................ ................................ ................................ ............... 24 7.2.8 read status register - 1 (05h) and read status register - 2 ( 3 5h) ................................ ......... 25 7.2.9 write status register (01h) ................................ ................................ ................................ ... 25 7.2.10 read data (03h) ................................ ................................ ................................ ................. 27 7.2.11 fast read (0bh) ................................ ................................ ................................ ................. 28 7.2.12 fast read dual output (3bh) ................................ ................................ ............................. 29 7.2.13 fast read quad output (6bh) ................................ ................................ ............................ 30 7.2.14 f ast read dual i/o (bbh) ................................ ................................ ................................ ... 31 7.2.15 fast read quad i/o (ebh) ................................ ................................ ................................ . 33 7.2.16 word read quad i/o (e7h) ................................ ................................ ................................ 35 7.2.17 octal word read quad i/o (e3h) ................................ ................................ ....................... 37 7.2.18 set burst with wrap (77h) ................................ ................................ ................................ ... 39 7.2.19 continuous read mode bits (m7 - 0) ................................ ................................ .................... 40 7.2.20 continuous read mode reset (ffh or ffffh) ................................ ................................ .. 40 7.2.21 page program (02h) ................................ ................................ ................................ ........... 41 7.2.22 quad input page program ( 3 2h) ................................ ................................ ......................... 42 7.2.23 sector erase (20h) ................................ ................................ ................................ .............. 42 7.2.24 32kb block erase (52h) ................................ ................................ ................................ ...... 44 7.2.25 64kb block erase (d8h) ................................ ................................ ................................ ..... 45 7.2.26 chip erase (c7h / 60h ) ................................ ................................ ................................ ....... 46 7.2.27 erase / program suspend (75h) ................................ ................................ ......................... 47 7.2.28 erase / program resume (7ah) ................................ ................................ .......................... 48 7.2.29 power - down (b9h) ................................ ................................ ................................ .............. 49 7.2.30 release power - down / device id (abh) ................................ ................................ ............. 50 7.2.31 read m anufacturer / device id (90h) ................................ ................................ ................. 52 7.2.32 read manufacturer / device id dual i/o (92h) ................................ ................................ ... 53 7.2.33 read manufacturer / device id qua d i/o (94h) ................................ ................................ .. 54 7.2.34 read unique id number (4bh) ................................ ................................ ........................... 55 7.2.35 read jedec id (9fh) ................................ ................................ ................................ ........ 56 7.2.36 read sfdp register (5ah) ................................ ................................ ................................ . 57 7.2.37 erase security registers (44h) ................................ ................................ ........................... 58 7.2.38 program security registers (42h) ................................ ................................ ....................... 59
- 4 - 7.2.39 read security registers (48h) ................................ ................................ ............................ 60 7.2.40 enable reset (66h) and reset (99h) ................................ ................................ .................. 61 8. electrical character istics ................................ ................................ .............................. 62 8.1 absolute maximum ratings (1) ................................ ................................ .......................... 62 8.2 operating ranges ................................ ................................ ................................ .............. 62 8.3 power - up power - down timing and requirements ................................ ........................... 63 8.4 dc electrical characteristics ................................ ................................ .............................. 64 8.5 ac measurement conditions ................................ ................................ ............................. 65 8.6 ac electrical characteristics ................................ ................................ .............................. 66 8.7 ac electrical characteristics (con td) ................................ ................................ ................. 67 8.8 serial output timing ................................ ................................ ................................ ........... 68 8.9 serial input timing ................................ ................................ ................................ .............. 68 8 .10 /hold timing ................................ ................................ ................................ ..................... 68 8.11 /wp timing ................................ ................................ ................................ ......................... 68 9. package specificatio n ................................ ................................ ................................ .......... 69 9.1 8 - pin soic 150 - mil (package code sn) ................................ ................................ ........... 69 9.2 8 - pin soic 208 - mil (package code ss) ................................ ................................ ........... 70 9.3 8 - pin pdip 300 - mil (package code da) ................................ ................................ ............ 71 9.4 8 - pad wson 6x5mm (package code zp) ................................ ................................ ........ 72 9.5 8 - pad uson 4x3 - mm (package code uu) ................................ ................................ ....... 73 9.6 8 - pad uson 4x4 - mm (package code uz) ................................ ................................ ....... 74 9.7 16 - pin soic 300 - mil (package code sf) ................................ ................................ .......... 74 9.8 24 - ball tfbga 8x6 - mm (package code tb, 5x5 - 1 ball array) ................................ ......... 76 9.9 24 - ball tfbga 8x6 - mm (package code tc, 6x4 ball array) ................................ ............ 76 10. ordering i nformation ................................ ................................ ................................ .......... 78 10.1 valid part numbers and top side marking ................................ ................................ ........ 79 11. revision history ................................ ................................ ................................ ...................... 80
publication release date: january 26, 2015 - 5 - revision j 1. general description the w 25q16d v ( 16m - bit) serial flash memory provide s a storage solution for systems with limited space, pins and power. the 25 q series offers flexibility and performance well beyond ordinary serial flash devices. they are ideal for code shadowin g to ram, executing code directly from d ua l/quad spi (xip ) and storing voice, text and data. the device operate s on a single 2.7 v to 3.6 v power supply with current consumption as low as 4 ma active and 1a for power - down. the w 25q16d v array is organized in to 8,192 programmable pages of 256 - bytes each. up to 256 bytes can be programmed at a time. pag es can be erased in groups of 16 ( 4kb sector erase), groups of 128 (32kb block erase), groups of 256 ( 64kb block erase) or the entire chip (chip erase). the w 25q 16d v has 512 erasable sectors and 32 erasable blocks respectively. the small 4kb sectors allow for greater flexibility in applications that require data and parameter storage. (see figure 2.) the w 25q16d v supports the standard serial peripheral interface (spi), and a high performance d ual /quad output as well as dual/quad i/o spi: serial clock, chip select, serial data i/o 0 (di), i/o1 (do), i/o2 (/wp), and i/o3 (/hold) . spi clock frequencies of up to 104 mhz are supported allowing equivalent clock rates of 2 08mhz ( 104mhz x 2) for dual i/o and 416mhz ( 104mhz x 4) for quad i/o when using the fast read dual/quad i/o instructions. these transfer rates can outperform standard asynchronous 8 and 16 - bit parallel flash memories. the continuous read mode allows for ef ficient memory access with as few as 8 - clocks of instruction - overhead to read a 24 - bit address, allowing true xip ( execute in place) operation. a hold pin, write protect pin and programmable write protect ion , with top or bottom array control, provide fur ther control flexibility. additionally, the device supports jedec standard manufacturer and device identification with a 64 - bit unique serial number . 2. features ? family of spiflash memories C w 25q16d v : 16m - bit / 2 m - byte ( 2,097,152 ) C 256 - byte per programmable page C standard spi: clk, /cs, di, do, /wp, /hold C dual spi: clk, /cs, io 0 , io 1 , /wp, /hold C quad spi: clk, /cs, io 0 , io 1 , io 2 , io 3 ? highest performance serial flash C 104 mhz dual spi / quad spi clocks C 208 / 416mhz equivalent dual/quad spi C 52mb /s cont inuous data transfer rate C up to 8x that of ordinary serial flash C more than 100,000 erase/program cycles C more than 20 - year data retention ? efficient continuous read mode C low instruction overhead C continuous read with 8/16/32/64 - byte wrap C as fe w as 8 clocks to address memory C allows true xip ( execute in place) operation C outperforms x16 parallel flash ? low power, wide temperature range C single 2.7 to 3.6 v supply C 4 ma active current, <1a power - down (typ.) C - 40c to + 85 c operating range ? flexib le architecture with 4kb sectors C uniform sector/block erase (4/32/64k - bytes ) C program one to 256 bytes C erase/program s uspend & resume ? advanced security & identification features C software and hardware write - protect C top/ bottom, 4kb complement array prot ection C power supply lock - down and otp protection C 64 - bit unique id for each device C d iscoverable parameter s (sfdp) register C 3x256 - byte security registers with otp lock s C volatile & non - volatile status register bits ? space efficient packaging (1 ) C 8 - pin soic 150/208 - mil C 8 - pad wson 6x5 - mm C 8 - pad uson 4x3mm / 4x4mm C 8 - pin pdip 300 - mil C 16 - pin soic 300 - mil C 24 - ball tfbga 8x6 - mm (6x4/5x5 ball array) C contact winbond for kgd and other option s note 1. some package types are special orders , pleas e contact winbond for ordering information .
- 6 - 3. package types and pi n configurations w 25q16d v is offered in an 8 - pin soic 150 - mil or 208 - mil (package code sn & ss), an 8 - pad wson 6x5 - mm (package code zp), an 8 - pad u son 4x3 - mm (package code uu ) , an 8 - pad u son 4x 4 - mm (package code u z ), an 8 - pin pdip 300 - mil (package code da), a 16 - pin soic 300 - mil (package code sf) and a 24 - ball 8x6 - mm tfbga ( 5x5 ball array - package code tb, 6x4 ball array C package code tc ) as shown in figure 1a - e respectively. package diagra ms and dimensions are illustrated at the end of this datasheet. 3.1 pin configuration soic 150 / 208 - mil figure 1a . w 25q16d v pin assignme nts, 8 - pin soic 1 50 / 208 - mil (package code sn, ss , sv, st ) 3.2 pad configuration wson 6x5 - mm / us on 4x3 - mm / uson 4x 4 - mm figure 1 b . w 25q16d v pad assignments, 8 - pad wson 6x5 - mm / uson 4x3 - mm (package code zp ,uu ,uz ) 1 2 3 4 8 7 6 5 /cs do (io 1 ) /wp (io 2 ) gnd vcc /hold (io 3 ) di (io 0 ) clk top view 1 2 3 4 /cs do (io 1 ) /wp (io 2 ) gnd vcc /hold (io 3 ) di (io 0 ) clk top view 8 7 6 5
publication release date: january 26, 2015 - 7 - revision j 3.3 pin configuration pdip 300 - mil figure 1c. w 25q16d v pin assignments, 8 - pin pdip (package code da) 3.4 pin desc ription soic 150/208 - mil, wson 6x5 - mm / uson 4x3 - mm / pdip 300 - mil pin no. pin name i/o function 1 /cs i chip select input 2 do ( io1 ) i/ o data output ( data input output 1)* 1 3 /wp ( io2 ) i /o write protect input ( data input output 2)* 2 4 gnd ground 5 di ( io0 ) i/o data i nput ( data input output 0)* 1 6 clk i serial clock input 7 /hold ( io3 ) i /o hold input ( data input output 3)* 2 8 vcc power supply *1 io0 and io1 are used for standard and dual spi instructions *2 io0 C io3 are used for quad spi instru ctions 1 2 3 4 8 7 6 5 /cs do (io 1 ) /wp (io 2 ) gnd vcc /hold (io 3 ) di (io 0 ) clk top view
- 8 - 3.5 pin configuration soic 300 - mil figure 1d. w 25q16d v pin assignments, 16 - pin soic 300 - mil (package code sf) 3.6 pin description soic 300 - mil p in no. p in name i/o function 1 /hold ( io3 ) i /o hold input ( data input output 3)* 2 2 vcc power supply 3 n/c no connect 4 n/c no connect 5 n/c no connect 6 n/c no connect 7 /cs i chip select input 8 do (io1) i/ o data out put (data input output 1)* 1 9 /wp ( io2 ) i /o write protect input ( data input output 2)* 2 10 gnd ground 11 n/c no connect 12 n/c no connect 13 n/c no connect 14 n/c no connect 15 di ( io0 ) i /o data input (data input output 0)* 1 16 clk i serial clock input *1 io0 and io1 are used for standard and dual spi instructions *2 io0 C io3 are used for quad spi instructions 1 2 3 4 /cs do (io 1 ) /wp (io 2 ) gnd vcc /hold (io 3 ) di (io 0 ) clk top view nc nc nc nc nc nc nc nc 5 6 7 8 10 9 11 12 13 14 15 16
publication release date: january 26, 2015 - 9 - revision j 3.7 ball configuration tfbga 8x6 - mm figure 1 e . w 25q16d v ball assignments, 24 - ball tfbga 8x6 - mm (package code tb or tc ) 3.8 ball description tfbga 8x6 - mm ball no. p in name i/o function b2 clk i serial clock input b3 gnd ground b4 vcc power supply c2 /cs i chip select input c4 /wp ( io2 ) i /o write protect input ( data input output 2)* 2 d2 do (io1) i/ o data out put (data input output 1)* 1 d3 di ( io0 ) i /o data input (data input output 0)* 1 d4 /hold ( io3 ) i /o hold input ( data input output 3)* 2 multiple nc no connect *1 io0 and io1 are used for standard and dual spi instructions *2 io0 C io3 are used for quad spi instructions d 1 / h o l d ( i o 3 ) d i ( i o 0 ) d o ( i o 1 ) / w p ( i o 2 ) d 2 d 3 d 4 n c e 1 n c n c n c e 2 e 3 e 4 n c f 1 n c n c n c f 2 f 3 f 4 n c a 1 n c n c n c a 2 a 3 a 4 n c b 1 v c c g n d c l k b 2 b 3 b 4 n c c 1 n c / c s c 2 c 3 c 4 n c t o p v i e w p a c k a g e c o d e t c d 1 / h o l d ( i o 3 ) d i ( i o 0 ) d o ( i o 1 ) / w p ( i o 2 ) d 2 d 3 d 4 n c e 1 n c n c n c e 2 e 3 e 4 n c b 5 n c n c n c a 2 a 3 a 4 n c b 1 v c c g n d c l k b 2 b 3 b 4 n c c 1 n c / c s c 2 c 3 c 4 n c t o p v i e w p a c k a g e c o d e t b c 5 n c d 5 n c e 5 n c a 5 n c
- 10 - 4. pin descriptions 4.1 chip select ( /cs ) the spi chip select ( /cs ) pin enables and disables device o peration. when /cs is high the device is deselected and the serial data output ( do, or io0, io1, io2, i o3 ) pin s are at high impedance. when deselected, the devices power consumption will be at standby levels unless an internal erase, program or write statu s register cycle is in progress. when /cs is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. after power - up, /cs must transition from high to low be fore a new instruction will be accepted. the /cs input must track the vcc supply level at power - up and power - down (see write protection and figure 3 9 ). if needed a pull - up resister on /cs can be used to accomplish this. 4.2 serial data input, output and ios (d i , d o and io0, io1, io2, io3) the w 25q16d v support s standard spi, dual spi and quad spi operation. standard spi instructions use the unidirectional d i (input) pin to serially write instructions, addresses or data to the device on the rising edge of the serial clock (clk) input pin. standard spi also uses the unidirectional do (output) to read data or status from the device on the falling edge of clk. dual and quad spi instruction s use the bidirectional io pins to serially write instructions, addresses o r data to the device on the rising edge of clk and read data or status from the device on the falling edge of clk. quad spi instructions require the non - volatile quad enable bit (qe) in status register - 2 to be set. when qe=1 , the /wp pin becomes i o 2 and / hold pin becomes io3. 4.3 write protect ( /wp ) the write protect ( /wp ) pin can be used to prevent the status register from being written. used in conjunction with the status registers block protect ( cmp, sec , tb, bp2, bp1 and bp0 ) bits and status register pro tect (srp) bits, a portion as small as a 4kb sector or the entire memory array can be hardware protected. the /wp pin is active low. when the qe bit of status register - 2 is set for q uad i/ o, the /wp pin function is not available since this pin is used for i o 2 . see figure 1a - e for the pin c onfiguration of quad i/o operation . 4.4 h old ( /hold ) the /hold pin allows the device to be paused while it is actively selected. when /hold is brought low, while /cs is low, the do pin will be at high impedance and signals on the di and clk pins will be ignored (dont care). when /hold is brought high, device operation can resume. the /hold function can be useful when multiple devices are sharing the same spi signals. the /hold pin is active low. when the qe bit of status regis ter - 2 is set for quad i/o, the /hold pin function is not available since this pin is used for io3. see figure 1a - e for the pin configuration of quad i/o operation. 4.5 serial clock (clk) the spi serial clock input (clk) pin provides the timing for serial input an d output operations. ("see spi operations")
publication release date: january 26, 2015 - 11 - revision j 5. block diagram figure 2 . w 25q16d v serial flash memory block diagram 003000h 0030ffh 002000h 0020ffh 001000h 0010ffh column decode and 256 - byte page buffer beginning page address ending page address w25q16dv spi command & control logic byte address latch / counter status register write control logic page address latch / counter do (io 1 ) di (io 0 ) /cs clk /hold (io 3 ) /wp (io 2 ) high voltage generators xx0f00h xx0fffh ? sector 0 (4kb) ? xx0000h xx00ffh xx1f00h xx1fffh ? sector 1 (4kb) ? xx1000h xx10ffh xx2f00h xx2fffh ? sector 2 (4kb) ? xx2000h xx20ffh ? ? ? xxdf00h xxdfffh ? sector 13 (4kb) ? xxd000h xxd0ffh xxef00h xxefffh ? sector 14 (4kb) ? xxe000h xxe0ffh xxff00h xxffffh ? sector 15 (4kb) ? xxf000h xxf0ffh block segmentation data security register 1 - 3 write protect logic and row decode 00ff00h 00ffffh ? block 0 (64kb) ? 000000h 0000ffh ? ? ? 07ff00h 07ffffh ? block 7 (64kb) ? 070000h 0700ffh 08ff00h 08ffffh ? block 8 (64kb) ? 080000h 0800ffh ? ? ? 0fff00h 0fffffh ? block 15 (64kb) ? 0f0000h 0f00ffh 10ff00h 10ffffh ? block 16 (64kb) ? 100000h 1000ffh ? ? ? 1fff00h 1fffffh ? block 31 (64kb) ? 1f0000h 1f00ffh 000000h 0000ffh sfdp register
- 12 - 6. functional descripti on 6.1 spi operations 6.1.1 standard spi instructions the w 25q16d v is accessed throu gh an spi compatible bus consisting of four signals: serial clock (clk), chip select ( /cs ), serial data input ( di ) and serial data output (do). standard spi instructions use the di input pin to serially write instructions, addresses or data to the device o n the rising edge of clk . the do output pin is used to read data or status from the device on the falling edge clk. spi bus operation mode 0 (0,0) and 3 (1,1) are supported. the primary difference between mode 0 and mode 3 concerns the normal state of the clk signal when the spi bus master is in standby and data is not being transferred to the serial flash. for mode 0 , the clk signal is normally low on the falling and rising edges of /cs. for mode 3 , the clk signal is normally high on the falling and risin g edges of /cs . 6.1.2 dual spi instructions the w 25q16d v support s dual spi operation when using the fast read dual output (3bh) and fast read dual i/o (bbh) instruction s . th ese instructions allow data to be transferred to or from the device at two to three times the rate of ordinary serial flash devices. the dual spi read i nstruction s are ideal for quickly downloading code to ram upon power - up (code - shadowing) or for execut ing non - speed - critical code directly from the spi bus (xip) . when using dual spi inst ructions , the di and do pins become bidirectional i/ o pins: io0 and io1. 6.1.3 quad spi instructions the w 25q16d v supports quad spi operation whe n using the fast read quad output (6bh) , fast read quad i/o (ebh) , word read quad i/o (e7h) and octal word rea d quad i/o (e3h) instructions . these instructions allow data to be transferred to or from the device four to six times the rate of ordinary serial flash. the quad read instructions offer a significant improvement in continuous and random access transfer r ates allowing fast code - shadowing to ram or execut ion directly from the spi bus (xip) . when using quad spi instructions the di and do pins become bidirectional io0 and io1 , and the /wp and /hold pins become io2 and io3 respectively. quad spi instructions r equire the non - volatile quad enable bit (qe) in status register - 2 to be set . 6.1.4 hold function for standard spi and dual spi operations, t he /hold signal allows the w 25q16d v operation to be paused while it is actively selected (when /cs is low). the /hold func tion may be useful in cases where the spi data and clock signals are shared with other devices. for example, consider if the page buffer was only partially written when a priority interrupt requires use of the spi bus. in this case the /hold function can s ave the state of the instruction and the data in the buffer so programming can resume where it left off once the bus is available again. the /hold function is only available for standard spi and dual spi operation, not during quad spi. to initiate a /hold condition, the device must be selected with /cs low. a /hold condition will activate on the falling edge of the /hold signal if the clk signal is already low. if the clk is not already low the /hold condition will activate after the next falling edge of cl k. the /hold condition will terminate on the rising edge of the /hold signal if the clk signal is already low. if the clk is not already low the /hold condition will terminate after the next falling edge of clk. during a /hold condition, the serial data ou tput (do) is high impedance, a nd serial data input (di ) and serial clock (clk) are ignored. the chip
publication release date: january 26, 2015 - 13 - revision j select ( /cs ) signal should be kept active (low) for the full duration of the /hold operation to avoid resetting the internal logic state of the device. 6.2 wri te protection applications that use non - volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. to address this concern , the w 25q16d v provides several means to protect th e data from inadvertent writes. 6.2.1 write protect features ? device resets when vcc is below threshold ? time delay write disable after power - up ? write enable/disable instructions and a ut omatic write disable after e rase or program ? software and hardware (/wp pin) w rite protection using status register ? write protection using power - down instruction ? lock down write protection until next power - up ? one time program (otp) write protection * * note : this feature is available upon special order. please contact winbond for details. upon power - up or at power - down , the w 25q16d v will maintain a reset condition while vcc is below the threshold value of v wi , (see power - up timing and voltage levels and figure 3 9 ). while reset, all operations are disabled and no instructions are r ecognized. during power - up and after the vcc voltage exceeds v wi , all program and erase related instructions are further disabled for a time delay of t puw . this includes the write enable, page program, sector erase, block erase, chip erase and the write st atus register instructions. note that the chip select pin ( /cs ) must track the vcc supply level at power - up until the vcc - min level and t vsl time delay is reached , and it must also track the vcc supply level at power - down to prevent adverse command sequenc e . if needed a pull - up resister on /cs can be used to accomplish this. after power - up the device is automatically placed in a write - disabled state with the status register write enable latch (wel) set to a 0. a write enable instruction must be issued befo re a page program, sector erase, block erase, chip erase or write status register instruction will be accepted. after completing a program, erase or write instruction the write enable latch (wel) is automatically cleared to a write - disabled state of 0. sof tware controlled write protection is facilitated using the write status register instruction and setting the status register protect (srp 0, srp1 ) and block protect ( cmp, sec, tb, bp2, bp1 and bp0 ) bits. these settings allow a portion as small as 4kb sector or the entire memory array to be configured as read only. used in conjunction with the write protect ( /wp ) pin, changes to the status register can be enabled or disabled under hardware control. see status register section for further information. additiona lly, the power - down instruction offers an extra level of write protection as all instructions are ignored except for the release power - down instruction.
- 14 - 7. status register s and instructions the read status register - 1 and status register - 2 instruction s can be used to provide status on the availability of the flash memory array, if the device is write enabled or disabled, t he state of write protection , quad spi s e tting , security register lock status and erase/program suspend status . the write status register in struction can be used to configure the device write protection features , quad spi sett i ng and security register otp lock . write access to the status register is controlled by the state of the non - volatile s tatus register protect bits (srp 0, srp1 ) , the writ e enable instruction, and during standard/dual spi operations, the /wp pin . 7.1 status register s 7.1.1 busy status (busy) busy is a read only bit in the status register (s0) that is set to a 1 state when the device is executing a page program, quad page program, se ctor erase, block erase, chip erase, write status register or erase/program security register instruction. during this time the device will ignore further instructions except for the read status register and erase /program suspend instruction (see t w , t pp , t se , t b e , and t c e in ac characteristics). when the program, erase or write status /security register instruction has completed, the busy bit will be cleared to a 0 state indicating the device is ready for further instructions. 7.1.2 write enable latch status (we l) write enable latch (wel) is a read only bit in the statu s register (s1) that is set to 1 after executing a write enable instruction. th e wel status bit is cleared to 0 when the device is write disabled. a write disable state occurs upon power - up or afte r any of the following instructions: write disable, page program, quad page program, sector erase, block erase, chip erase, write status register , erase security register and program security register . 7.1.3 block protect bits (bp2, bp1, bp0) the block protect b its (bp2, bp1, bp0 ) are non - volatile read/write bits in the status register (s4, s3, and s2 ) that provide write protection control and status. block protect bits can be set using the write status register instruction (see t w in ac characteristics). all, no ne or a portion of the memory array can be protected from program and erase instructions (see status register memory protection table). the factory default setting for the block protection bits is 0, none of the array protected. 7.1.4 top/bottom block protect b it (tb) the non - volatile top/bottom bit (tb) controls if the block protect bits (bp2, bp1, bp0) protect from the top (tb=0) or the bottom (tb=1) of the array as shown in the status register memory protection table. the f actory default setting is tb=0. the tb bit can be set with the write status register instruction depending on the state of the srp0, srp1 and wel bits. 7.1.5 sector /block protect bit (sec) the non - volatile sector /block p rotect bit (sec) controls if the block protect bits (bp2, bp1, bp0) protect either 4kb sectors (sec=1) or 64kb blocks (sec=0) in the top (tb=0) or the bottom (tb=1) of the array as shown in the status register memory protection table. the default setting is sec =0. 7.1.6 complement protect bit (cmp) the c omplement p rotect bit (cmp) is a non - volatile read/write bit in the status register (s14). it is used in conjunction with sec, tb, bp2, bp1 and bp0 bits to provide more flexibility for the array protection. once cmp is set to 1, previous array protection set by sec, tb, bp2, bp1 and bp0 will be reversed. for instance, when cmp=0, a top 4kb sector can be protected while the rest of the array is not; when
publication release date: january 26, 2015 - 15 - revision j cmp=1, the top 4kb sector will become unprotected while the rest of the array become read - only. please refer to the status register memor y protection table for details. the default setting is cmp =0. 7.1.7 status register protect bits (srp 1 , srp 0 ) the status register protect bits (srp 1 and srp0 ) are non - volatile read/write bits in the status register (s8 and s7). the srp bits control the method o f write protection: s oftware p rotection, h ardware p rotection, p ower s upply l ock - d own or o ne t ime p rogrammable (otp) p rotection. srp1 srp0 /wp status register description 0 0 x software protection /wp pin has no control. the status register can be written to after a write enable instruction , wel=1 . [factory default] 0 1 0 hardware protect ed when /wp pin is low the status register locked and can not be written to . 0 1 1 hardware unprotected when /wp pin is high the status register is unlocked and can be written to after a write enable instruction , wel=1. 1 0 x power supply lock - down status register is protected and can not be written to again until the next power - down , power - up cycle . ( 1 ) 1 1 x one time program ( 2 ) status register is permanently protect ed and can not be written to. note s : 1. when srp1, srp0 = (1, 0), a power - down, power - up cycle will change srp1, srp0 to (0, 0) state. 2 . this feature is available upon special order. please contact winbond for details. 7.1.8 erase/program suspend status (sus ) the suspend status bit is a read only bit in the status register (s15) that is set to 1 after executing a erase/program suspend (75h) instruction. the sus status bit is cleared to 0 by erase/program resume (7ah) instr uction as well as a power - down, power - up cycle. 7.1.9 security register lock bits (lb3, lb2, lb1 ) the security register lock bits (lb3, lb2, lb1) are non - volatile one time program (otp) bits in status register (s13, s12, s11) that provide the write protect control and status to the security registe rs . the default state of lb [ 3 :1] is 0, security registers are unlocked. lb [3:1] can be set to 1 individually using the write status register instruction. lb [3:1] are one time programmable (otp), once its set to 1, the corresponding 256 - byte security regis ter will become read - only permanently. 7.1.10 quad enable bit ( qe ) the quad enable (qe ) bit is a non - volatile read/write bit in the status register (s 9 ) that allow s quad spi operation . when the qe bit is set to a 0 state (factory default) , the /wp pin and /h old a re enabled . when the qe bit is set to a 1 , the quad io2 and i o3 pins are enabled , and /wp and /hold functions are disabled . warning: if the /wp or /hold pins are tied directly to the power supply or ground during standard spi or dual spi operation, the qe bit should never be set to a 1 .
- 16 - figure 3 a . status register - 1 figure 3 b . status register - 2 s7 s6 s5 s4 s3 s2 s1 s0 srp0 sec tb bp2 bp1 bp0 wel busy status register protect 0 (non - volatile) sector protect (non - volatile) top/bottom protect (non - volatile) block protect bits (non - volatile) write enable latch erase/write in progress s7 s6 s5 s4 s3 s2 s1 s0 srp0 sec tb bp2 bp1 bp0 wel busy status register protect 0 (non - volatile) sector protect (non - volatile) top/bottom protect (non - volatile) block protect bits (non - volatile) write enable latch erase/write in progress s15 s14 s13 s12 s11 s10 s9 s8 sus cmp lb3 lb2 lb1 (r) qe srp1 suspend status complement protect (non - volatile) security register lock bits (non - volatile otp) quad enable (non - volatile) status register protect 1 (non - volatile) reserved s15 s14 s13 s12 s11 s10 s9 s8 sus cmp lb3 lb2 lb1 (r) qe srp1 suspend status complement protect (non - volatile) security register lock bits (non - volatile otp) quad enable (non - volatile) status register protect 1 (non - volatile) reserved
publication release date: january 26, 2015 - 17 - revision j 7.1.11 status register memory protection (cmp = 0) status register (1) w 25q16d v ( 16m - bit) memory protecti on (3) sec tb bp2 bp1 bp0 pro tected block(s) protected addresses protected density protected portion (2) x x 0 0 0 none none none none 0 0 0 0 1 31 1 f0000h C 1 fffffh 64kb upper 1/32 0 0 0 1 0 30 and 31 1 e0000h C 1 fffffh 128kb upper 1/16 0 0 0 1 1 28 thru 31 1 c0000h C 1 fffffh 256kb upper 1/8 0 0 1 0 0 24 thru 31 1 80000h C 1 fffffh 512kb upper 1/4 0 0 1 0 1 16 thru 31 1 00000h C 1 fffffh 1mb upper 1/2 0 1 0 0 1 0 000000h C 00ffffh 64kb lower 1/32 0 1 0 1 0 0 and 1 000000h C 01ffffh 128kb lower 1/16 0 1 0 1 1 0 thru 3 000000h C 03fff fh 256kb lower 1/8 0 1 1 0 0 0 thru 7 000000h C 07ffffh 512kb lower 1/4 0 1 1 0 1 0 thru 15 000000h C 0fffffh 1mb lower 1/2 x x 1 1 x 0 thru 31 000000h C 1f ffffh 2mb all 1 0 0 0 1 31 1ff000 h C 1f ffffh 4kb u C 1/512 1 0 0 1 0 31 1fe000 h C 1f ffffh 8kb u C 1/ 256 1 0 0 1 1 31 1fc000 h C 1f ffffh 16kb u C 1/ 128 1 0 1 0 x 31 1f8000 h C 1f ffffh 32kb u C 1/ 64 1 1 0 0 1 0 000000h C 000fffh 4kb l C 1/512 1 1 0 1 0 0 000000h C 001fffh 8kb l C 1/ 256 1 1 0 1 1 0 000000h C 003fffh 16kb l C 1/ 128 1 1 1 0 x 0 0000 00h C 007fffh 32kb l C 1/ 64 note s : 1. x = dont care 2. l = lower; u = upper 3. if any erase or program command specifies a memory region that contains protected data portion, this command will be ignored.
- 18 - 7.1.12 status register memory protection (cmp = 1) status regi ster (1) w 25q16d v (16m - bit) memory protecti on (3) sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion (2) x x 0 0 0 0 thru 31 00 0000h C 1 fffffh all all 0 0 0 0 1 0 thru 30 00 0000h C 1 effffh 1,984 kb lower 31/32 0 0 0 1 0 0 thru 29 00 0000h C 1 dffffh 1,920 kb lower 15/16 0 0 0 1 1 0 thru 27 00 0000h C 1 bffffh 1,792 kb lower 7/8 0 0 1 0 0 0 thru 23 00 0000h C 1 7ffffh 1,536 kb lower 3/4 0 0 1 0 1 0 thru 15 0 00000h C 0 fffffh 1mb lower 1/2 0 1 0 0 1 1 thru 31 010000h C 1ff fffh 1,984kb upper 31/32 0 1 0 1 0 2 and 31 020000h C 1fffffh 1,920kb upper 15/16 0 1 0 1 1 4 thru 31 040000h C 1fffffh 1,792kb upper 7/8 0 1 1 0 0 8 thru 31 080000h C 1fffffh 1,536kb upper 3/4 0 1 1 0 1 16 thru 31 100000h C 1fffffh 1mb upper 1/2 x x 1 1 x none none none none 1 0 0 0 1 0 thru 31 000 000 h C 1f efffh 2,04 4kb l C 511/512 1 0 0 1 0 0 thru 31 000 000 h C 1f dfffh 2,040 kb l C 255/256 1 0 0 1 1 0 thru 31 000 000 h C 1f bfffh 2,032 kb l C 127/128 1 0 1 0 x 0 thru 31 000 000 h C 1f 7fffh 2,016 kb l C 63/64 1 1 0 0 1 0 thru 31 00 1 000h C 1ff fffh 2,04 4kb u C 511/512 1 1 0 1 0 0 thru 31 00 2 000h C 1ff fffh 2,040 kb u C 255/256 1 1 0 1 1 0 thru 31 00 4 000h C 1ff fffh 2,032 kb u C 127/128 1 1 1 0 x 0 thru 31 00 8 000h C 1ff fffh 2,016 kb u C 63/64 note s : 1. x = do nt care 2. l = lower; u = upper 3. if any erase or program command specifies a memory region that contains protected data portion, this command will be ignored.
publication release date: january 26, 2015 - 19 - revision j 7.2 instructions the instruction set of the w 25q16d v consists of thirty five basic instructions that a re fully controlled through the spi bus (see instruction set table 1 - 3 ). instructions are initiated with the falling edge of chip select (/cs) . the first byte of data clo cked into the di input provides the i nstruction code. data on the di input is sampled o n the rising edge of clock with most significant bit (msb) first. instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (dont care), and in some cases, a combination. instructions ar e completed with the rising edge of edge /cs . clock relative timing diagrams for each instruction are included in figures 4 through 3 7 . all read instructions can be completed after any clocked bit. however, all instructions that write, program or erase mus t complete on a byte boundary ( / cs driven high after a full 8 - bits have been clocked) otherwise the instruction will be ignor ed. this feature further protects the device from inadvertent writes. additionally, while the memory is being programmed or erased, or when the status register is being written, all instructions except for read status register will be ignored until the program or erase cycle has completed. 7.2.1 manufacturer and device identification manufacturer id (m f 7 - m f 0) winbond serial flash ef h device id (id7 - id0) (id15 - id0) instruction abh, 90h 9fh w 25q16d v 1 4 h 4 01 5 h
- 20 - 7.2.2 instruction set table 1 (erase, program instructions) ( 1 ) instruction name byte 1 ( code ) byte 2 byte 3 byte 4 byte 5 byte 6 write enable 06h write enable for volatile stat us register 50h write disable 04h read status register - 1 05h (s7 C s0) ( 2 ) read status register - 2 35h (s 15 - s 8 ) ( 2 ) write status register 01h ( s7 C s0 ) (s 15 - s8) page program 02h a23 C a16 a15 C a8 a7 C a0 (d7 C d0) quad page program 3 2h a23 C a16 a15 C a8 a7 C a0 (d7 C d0 , ) (3) sector erase (4kb) 20 h a23 C a16 a15 C a8 a7 C a0 block erase (32kb) 52h a23 C a16 a15 C a8 a7 C a0 block erase ( 6 4kb) d8 h a23 C a16 a15 C a8 a7 C a0 chip erase c7h /60h erase / program suspend 75h erase / program resume 7ah power - down b9h c ontinuous read mode reset (4) ffh ffh notes: 1. data bytes are shifted with most significant bit first. byte fields with data in parenthesis () indicate data being read from the device on the do pin. 2. the status register contents will repeat continuousl y until /cs terminates the instruction. 3. quad page program input data : io0 = (d4, d0, ) io1 = (d5, d1, ) io2 = (d6, d2, ) io3 = (d7, d3, ) 4. this instruction is recommended w hen using the dual or quad continuous read mode feature. see section 7. 2. 1 9 & 7. 2. 20 for more information.
publication release date: january 26, 2015 - 21 - revision j 7.2.3 instruction set table 2 ( read instructions) instruction name byte 1 ( code ) byte 2 byte 3 byte 4 byte 5 byte 6 read data 03h a23 - a16 a15 - a8 a7 - a0 (d7 - d0) fast read 0bh a23 - a16 a15 - a8 a7 - a 0 dummy (d7 - d0) fast read dual output 3bh a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0 , ) (1) fast read quad output 6bh a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0 , ) (3) fast read dual i/o bbh a23 - a 8 (2) a7 - a0, m7 - m0 (2) (d7 - d0 , ) (1) fast read quad i/o ebh a23 - a0, m7 - m0 (4 ) ( x,x,x,x, d7 - d0 , ) (5) (d7 - d0, ) (3) word read quad i/o (7) e7h a23 - a0, m7 - m0 (4) ( x,x, d7 - d0 , ) (6) (d7 - d0, ) (3) octal word read quad i/o (8) e3h a23 - a0, m7 - m0 (4) (d7 - d0, ) (3) set burst with wrap 77h xxxxxx, w6 - w4 (4) notes : 1 . dual output data i o0 = (d6, d4, d2, d0) io1 = (d7, d5, d3, d1) 2 . dual input address io0 = a22, a20, a18, a16, a14, a12, a10, a8 a6, a4, a2, a0, m6, m4, m2, m0 io1 = a23, a21, a19, a17, a15, a13, a11, a9 a7, a5, a3, a1, m7, m5, m3, m1 3. quad output data io0 = (d4, d0, ..) io1 = (d5, d1, ..) io2 = (d6, d2, ..) io3 = (d7, d3, ..) 4. quad input address set burst with wrap input io0 = a20, a16, a12, a8, a4, a0, m4, m0 io0 = x, x, x, x, x, x, w4, x io1 = a21, a17, a13, a9, a5, a1, m5, m1 io1 = x, x, x, x, x, x, w5, x io2 = a22, a18, a14, a10, a6, a2, m6, m2 io2 = x, x, x, x, x, x, w6, x io3 = a23, a19, a15, a11, a7, a3, m7, m3 io3 = x, x, x, x, x, x, x, x 5 . fast read quad i/o data io0 = (x, x, x, x, d4, d0, ..) io1 = (x, x, x, x, d5, d1, ..) io2 = (x, x, x, x, d6, d2, ..) io3 = (x, x, x, x, d7, d3, ..) 6. word read quad i/o data io0 = (x, x, d4, d0, ..) io1 = (x, x, d5, d1, ..) io2 = (x, x, d6, d2, ..) io3 = (x, x, d7, d3, ..) 7. the lowest address bit must be 0. ( a0 = 0 ) 8. the lowest 4 address bits must be 0. ( a0, a1, a2, a3 = 0 )
- 22 - 7.2.4 instruction set table 3 (id, security instructions) instruction name byte 1 ( code ) byte 2 byte 3 byte 4 byte 5 byte 6 release power down / device id abh dummy dumm y dummy (id7 - id0) ( 1 ) manufacturer/ device id ( 2 ) 90h dummy dummy 00h (m f 7 - m f 0) (id7 - id0) manufacturer/device id by dual i/o 92h a23 - a8 a7 - a0, m[7:0] (mf[7:0], id[7:0]) manufacture/device id by quad i/o 94h a23 - a0, m[7:0] xxxx, (mf[7:0], id[7:0]) (mf[7: 0], id[7:0], ) jedec id 9fh (m f 7 - m f 0) manufacturer (id15 - id8) memory type (id7 - id0) capacity read unique id 4bh dummy dummy dummy d ummy (id63 - id0) read sfdp register 5ah 00h 00h a7 C a0 dummy (d7 - 0) erase security registers (3) 44h a23 C a16 a15 C a8 a7 C a0 program security registers (3) 42h a23 C a16 a15 C a8 a7 C a0 (d7 - 0) (d7 - 0) read security registers (3) 48h a23 C a16 a15 C a8 a7 C a0 dummy (d7 - 0) enable reset 66h reset 99h notes: 1. the device id will repeat continuously until /cs terminates the instruct ion. 2. see manufacturer and device identification table for device id information. 3. security register address: security register 1 : a23 - 16 = 00h ; a15 - 8 = 10h ; a7 - 0 = byte address security register 2 : a23 - 16 = 00h ; a15 - 8 = 20h ; a7 - 0 = byte address securi ty register 3 : a23 - 16 = 00h ; a15 - 8 = 30h ; a7 - 0 = byte address
publication release date: january 26, 2015 - 23 - revision j 7.2.5 write enable (06h) the write enable instruction (figure 4) sets the write enable latch (wel) bit in the status register to a 1. the wel bit must be set prior to every page program, quad pag e program, sector erase, block erase, chip erase, write status register and erase/program security registers instruction. the write enable instruction is entered by driving /cs low, shifting the instruction code 06h into the data input (di) pin on the ri sing edge of clk, and then driving /cs high. figure 4. write enable instruction sequence diagram 7.2.6 write enable for volatile status register (50h) the non - volatile status register bits described in section 7 .1 can also be written to as volatile bits. this gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non - volatile bit write cycles or affecting the endurance of the status register non - volatile bits. to write the volatile values into the status register bits, the write enable for volatile status register (50h) instruction must be issued prior to a write status register (01h) instruction. write enable for volatile status register instruction (figure 5) wi ll not set the write enable latch (wel) bit, it is only valid for the write status register instruction to change the volatile status register bit values. figure 5. write enable for volatile status register instruction sequenc e diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (06h) high impedance /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (50h) high impedance
- 24 - 7.2.7 write disable (04h) the write disable instruction (figure 6) resets the write enable latch (wel) bit in the status register to a 0. the write disable instruction is entered by driving /cs low, shifting the instruction code 04h into the di pin a nd then driving /cs high. note that the wel bit is automatically reset after power - up and upon completion of the write status register, erase/program security registers, page program, quad page program, sector erase, block erase and chip erase instructions . write disable instruction can also be used to invalidate the write enable for volatile status register instruction. figure 6. write disable instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (04h) high impedance
publication release date: january 26, 2015 - 25 - revision j 7.2.8 read status register - 1 (05h) and read status register - 2 ( 3 5h) the read status register instructions allow the 8 - bit status registers to be read. the instruction is entered by driving /cs low and shifting the instruction code 05h for status r egister - 1 or 35h for status r egister - 2 into the di pin on the risi ng edge of clk. the status register bits are then shifted out on the do pin at the falling edge of clk with most significant bit (msb) first as shown in figure 7. the status register bits are shown in figure 3a and 3b and include the busy, wel, bp2 - bp0, tb , sec, srp0, srp1, qe , lb[3:1] , cmp and sus bits (see status register section earlier in this datasheet). the read status register instruction may be used at any time, even while a program, erase or write status register cycle is in progress. this allows the busy status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. the status register can be read continuously, as shown in figure 7. the instruction is completed by driving /cs high. figure 7. r ead status register instruction sequence diagram 7.2.9 write status register (01h) the write status register instruction allows the status register to be written. only non - volatile status register bits srp0, sec, tb, bp2, bp1, bp0 (bits 7 thru 2 of status regist e r - 1) and cmp, lb3, lb2, lb1 , qe, srp1 (bits 14 thru 8 of status register - 2) can be written to. all other status register bit locations are read - only and will not be affected by the write s tatus register instruction. lb[3:1] are non - volatile otp bits, once it is set to 1, it can not be cleared to 0. the status register bits are shown in figure 3 and described in 7 .1. to write non - volatile status register bits, a standard write enable (06h) instruction must previously have been executed for the device to acc ept the write status register instruction (status register bit wel must equal 1). once write enabled, the instruction is entered by driving /cs low, sending the instruction code 01h, and then writing the status register data byte as illustrated in figure 8. to write volatile status register bits, a write enable for volatile status register (50h) instruction must have been executed prior to the write status register instruction (status register bit wel remains 0). howe ver, srp1 and lb3, lb2, lb1 can not be changed from 1 to 0 because of the otp protection for these bits. upon power off, the volatile status register bit values will be lost, and the non - volatile status register bit values will be restored when power on again. /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (05h or 35h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 status register 1 or 2 out status register 1 or 2 out * * = msb *
- 26 - to complete the write status register instruction, the /cs pin must be driven high after the eighth or sixteenth bit of data that is clocked in. if this is not done the write status register instruction will not be executed. if /cs is driven high after the eighth clock (compatible wi th the 25x series) the cmp and qe bits will be cleared to 0. during non - volatile status register write operation (06h combined with 01h), after /cs is driven high, the self - timed write status register cycle will commence for a time duration of t w (see ac c haracteristics). while the write status register cycle is in progress, the read status register instruction may still be accessed to check the status of the busy bit. the busy bit is a 1 during the write status register cycle and a 0 when the cycle is fini shed and ready to accept other instructions again. after the write status register cycle has finished, the write enable latch (wel) bit in the status register will be cleared to 0. during volatile status register write operation (50h combined with 01h), af ter /cs is driven high, the status register bits will be refreshed to the new values within the time period of t shsl2 (see ac characteristics). busy bit will remain 0 during the status register bit refresh period. please refer to 7 .1 for detailed status re gister bit descriptions. factory default for all status register bits are 0. figure 8. write status register instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (01h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 status register 1 in status register 2 in mode 0 mode 3 * * = msb *
publication release date: january 26, 2015 - 27 - revision j 7.2.10 read data (03h) the read data instruction allows one or more data bytes to be sequential ly read from the memory. the instruction is initiated by driving the /cs pin low and then shifting the instruction code 03h followed by a 24 - bit address (a23 - a0) into the di pin. the code and address bits are latched on the rising edge of the clk pin. a fter the address is received, the data byte of the addressed memory location will be shifted out on the do pin at the falling edge of clk with most significant bit (msb) first. the address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. this means that the entire memory can be accessed with a single instruction as long as the clock continues. the instruction is completed by driving /cs high. the read data instruction se quence is shown in figure 9. if a read data instruction is issued while an erase, program or write cycle is in process (busy=1) the instruction is ignored and will not have any effects on the current cycle. the read data instruction allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). figure 9. read data instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (03h) high impedance 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 7 6 5 4 3 2 1 0 7 24-bit address 23 22 21 3 2 1 0 data out 1 * * = msb *
- 28 - 7.2.11 fast read (0bh) the fast read instruction is similar to the read data instruction except that it can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accomplished by adding eight dummy clocks after the 24 - bit address as shown in figure 10. the dummy clocks allow the devices internal circuits additional time for setting up t he initial address. during the dummy clocks the data value on the do pin is a dont care. figure 10. fast read instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (0bh) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 dummy clocks high impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 data out 2 * 7 6 5 4 3 2 1 0 * 43 31 0 = msb *
publication release date: january 26, 2015 - 29 - revision j 7.2.12 fast read dual output (3bh) the fast read dual output (3bh) instruction is similar to the standard fast read (0bh) instruction except that data is output on two pins; io 0 and io 1 . this allows data to be transferred from the w 25q16d v at twice the rate of standard spi devices. the fast read dual output instruction is ideal for quickly downloading code from flash t o ram upon power - up or for applications that cache code - segments to ram for execution. similar to the fast read instruction, the fast read dual output instruction can operate at the highest possible frequency of f r (see ac electrical characteristics). thi s is accomplished by adding eight dummy clocks after the 24 - bit address as shown in figure 11. the dummy clocks allow the device's internal circuits additional time for setting up the initial address. the input data during the dummy clocks is dont care . however, the io 0 pin should be high - impedance prior to the falling edge of the first data out clock. figure 11. fast read dual output instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (3bh) high impedance 8 9 10 28 29 30 32 33 34 35 36 37 38 39 6 4 2 0 24-bit address 23 22 21 3 2 1 0 * * 31 31 /cs clk di (io 0 ) do (io 1 ) dummy clocks 0 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 7 5 3 1 high impedance 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 io 0 switches from input to output 6 7 data out 1 * data out 2 * data out 3 * data out 4 = msb *
- 30 - 7.2.13 fast read quad output (6bh) the fast read quad output (6bh ) instruction is similar to the fast read dual output (3bh) instruction except that data is output on four pins, io 0 , io 1 , io 2 , and io 3 . a quad enable of status register - 2 must be executed before the device will accept the fast read quad output instruction (status register bit qe must equal 1 ) . the fast read quad output instruction allows data to be transferred from the w 25q16d v at four times the rate of standard spi devices. the fast read quad output instruction can operate at the highest possible frequen cy of f r (see ac electrical characteristics). this is accomplished by adding eight dummy clocks after the 24 - bit address as shown in figure 12. the dummy clocks allow the device's internal circuits additional time for setting up the initial address. the input data during the dummy clocks is dont care. however, the io pins should be high - impedance prior to the falling edge of the first data out clock. figure 12. fast read quad output instruction sequence diagram /cs clk mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (6bh) high impedance 8 9 10 28 29 30 32 33 34 35 36 37 38 39 4 0 24-bit address 23 22 21 3 2 1 0 * 31 31 /cs clk dummy clocks 0 40 41 42 43 44 45 46 47 5 1 high impedance 4 5 byte 1 high impedance high impedance 6 2 7 3 high impedance 6 7 high impedance 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 byte 2 byte 3 byte 4 io 0 switches from input to output io 0 io 1 io 2 io 3 io 0 io 1 io 2 io 3 = msb *
publication release date: january 26, 2015 - 31 - revision j 7.2.14 f ast read dual i/o (bbh) the fast read dual i/o (bbh) instruction allows for improved random access while maintaining two io pins, io 0 and io 1 . it is similar to the fast read dual output (3bh) instruction but with the capability to input the address bits (a23 - 0) two bits per clock. this r educed instruction overhead may allow for code execution (xip) directly from the d ua l spi in some applications. fast read dual i/o with continuous read mode the fast read dual i/o instruction can further reduce instruction overhead through setting the c ontinuous read mode bits (m7 - 0) after the input address bits (a23 - 0), as shown in figure 1 3a . the upper nibble of the (m7 - 4) controls the length of the next fast read dual i/o instruction through the inclusion or exclusion of the first byte instruction co de. the lower nibble bits of the (m3 - 0) are dont care (x). however, the io pins should be high - impedance prior to the falling edge of the first data out clock. if the continuous read mode bits m5 - 4 = (1,0), then the next fast read dual i/o instructio n ( after /cs is raised and then lowered) does not require the bbh instruction code, as shown in figure 1 3b. this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if the conti nuous read mode bits m5 - 4 do not equal to (1,0), the next instruction ( after /cs is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. a continuous read mode reset instruction can also be used to reset (m7 - 0) before issuing normal instructions (see 7 .2.20 for detail descriptions). figure 1 3 a . fast read dual i/ o instruction sequence ( initial instruction or previous m 5 - 4 ? 10 ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (bbh) 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 * * 23 /cs clk di (io 0 ) do (io 1 ) 0 32 33 34 35 36 37 38 39 7 5 3 1 * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * ios switch from input to output 6 7 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 16 17 18 20 21 22 19 23 1 a23-16 a15-8 a7-0 m7-0 byte 1 byte 2 byte 3 byte 4 = msb * *
- 32 - figure 1 3 b . fast read dual i/ o instruction sequence ( previous instruc tion set m5 - 4 = 10 ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 * * 15 /cs clk di (io 0 ) do (io 1 ) 0 7 5 3 1 * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * ios switch from input to output 6 7 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 1 a23-16 a15-8 a7-0 m7-0 byte 1 byte 2 byte 3 byte 4 0 1 2 3 4 5 6 7 16 17 18 20 21 22 19 23 * = msb *
publication release date: january 26, 2015 - 33 - revision j 7.2.15 fast read quad i/o (ebh) the fast read quad i/o (ebh) instruction is similar to the fast read dual i/o (bbh) instruction except that address and data bits are input and output through four pins io 0 , io 1 , io 2 and io 3 and four dummy c lock are required prior to the data output . the quad i/o dramatically reduces instruction overhead allowing faster random access for code execution (xip) directly from the quad spi. the quad e nable bit (qe) of status register - 2 must be set to enable the fa st r ead quad i/o instruction . fast read quad i/o with continuous read mode the fast read quad i/o instruction can further reduce instruction overhead through setting the continuous read mode bits (m7 - 0) after the input address bits (a23 - 0), as shown in figure 14 a . the upper nibble of the (m7 - 4) controls the length of the next fast read quad i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3 - 0) are dont care (x). however, the io pins should be high - impedance prior to the falling edge of the first data out clock. if the continuous read mode bits m5 - 4 = (1,0), then the next fast read quad i/o instruction ( after /cs is raised and then lowered) does not require the ebh instruction code , as shown in figure 1 4b. this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if the continuous read mode bits m5 - 4 do not equal to (1,0), the next instruction ( after /cs is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. a continuous read mode reset instruction can also be used to reset (m7 - 0) before issuing normal instructions (see 7 .2.20 for detail descriptions). figure 1 4 a . fast read quad i/ o instruction sequence ( initial instruction or previous m 5 - 4 ? 10 ) m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 16 17 18 19 20 21 22 23 dummy dummy instruction (ebh)
- 34 - figure 1 4 b . fast read quad i/ o instruction s equence ( previous instruction set m5 - 4 = 10 ) fast read quad i/o with 8/16/32/64 - byte wrap around the fast read quad i/o instruction can also be used to access a specific portion within a page by issuing a set burst with wrap command prior to ebh. the set burst with wrap command can either enable or disable the wrap around feature for the following ebh commands. when wrap around is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64 - byte section of a 256 - byte page. the out put data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64 - byte section, the output will wrap around to the beginning boundary automatically until /cs is pulled high to terminate the command. the burst with wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64 - byte) of data without issuing multiple read commands. the set burst with wrap instru ction allows three wrap bits, w6 - 4 to be set. the w4 bit is used to enable or disable the wrap around operation while w6 - 5 are used to specify the length of the wrap around section within a page. see 7 .2.18 for detail descriptions. m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 dummy dummy
publication release date: january 26, 2015 - 35 - revision j 7.2.16 word read quad i/o (e7h) the word read quad i/o (e7h) instruction is similar to the fast read quad i/o (ebh) instruction except that the lowest address bit (a0) must equal 0 and only two dummy clocks are required prior to the data output. the quad i/o dramatically reduces i nstruction overhead allowing faster random access for code execution (xip) directly from the quad spi. the quad e nable bit (qe) of status register - 2 must be set to enable the word r ead quad i/o instruction . word read quad i/o with continuous read mode th e word read quad i/o instruction can further reduce instruction overhead through setting the continuous read mode bits (m7 - 0) after the input address bits (a23 - 0), as shown in figure 15 a . the upper nibble of the (m7 - 4) controls the length of the next fas t read quad i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3 - 0) are dont care (x). however, the io pins should be high - impedance prior to the falling edge of the first data out clock . if the continuous read mode bits m5 - 4 = (1,0), then the next fast read quad i/o instruction ( after /cs is raised and then lowered) does not require the e7h instruction code, as shown in figure 1 5b. this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if the continuous read mode bits m5 - 4 do not equal to (1,0), the next instruction ( after /cs is raised and then lowered) requires the first byte instruction code, thus retu rning to normal operation. a continuous read mode reset instruction can also be used to reset (m7 - 0) before iss uing normal instructions (see 7 .2.20 for detail descriptions). figure 1 5 a . word read qua d i/ o instruction sequence ( initial instruction or previous m 5 - 4 ? 10 ) m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 16 17 18 19 20 21 dummy instruction (e7h)
- 36 - figure 1 5 b . word read quad i/ o instruction sequence ( previous instruction set m5 - 4 = 10 ) word read quad i/o with 8/16/32/6 4 - byte wrap around the word read quad i/o instruction can also be used to access a specific portion within a page by issuing a set burst with wrap command prior to e7h. the set burst with wrap command can either enable or disable the wrap around fea ture for the following e7h commands. when wrap around is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64 - byte section of a 256 - byte page. the output data starts at the initial address specified in the instruction, once it rea ches the ending boundary of the 8/16/32/64 - byte section, the output will wrap around to the beginning boundary automatically until /cs is pulled high to terminate the command. the burst with wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64 - byte) of data without issuing multiple read commands. the set burst with wrap instruction allows three wrap bits, w6 - 4 to be set. the w4 bit is used to enable or disable the wrap around operation while w6 - 5 are used to specify the length of the wrap arou nd section within a page. see 7 .2.18 for detail descriptions. m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 4 0 5 1 6 2 7 3 a15-8 a7-0 4 0 5 1 6 2 7 3 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 5 6 7 ios switch from input to output byte 3 8 9 10 11 12 13 dummy
publication release date: january 26, 2015 - 37 - revision j 7.2.17 octal word read quad i/o (e3h) the octal word read quad i/o (e3h) instruction is similar to the fa st read quad i/o (ebh) instruction except that the lower four address bits (a0, a1, a2, a3) must equal 0. as a result, the dummy clocks are not required, which further reduces the instruction overhead allowing even faster random access for code execution ( xip). the quad enable bit (qe) of status register - 2 must be set to enable the octal word read quad i/o instruction. octal word read quad i/o with continuous read mode the octal word read quad i/o instruction can further reduce instruction overhead throu gh setting the continuous read mode bits (m7 - 0) after the input address bits (a23 - 0), as shown in figure 16a. the upper nibble of the (m7 - 4) controls the length of the next octal word read quad i/o instruction through the inclusion or exclusion of the fi rst byte instruction code. the lower nibble bits of the (m3 - 0) are dont care (x). however, the io pins should be high - impedance prior to the falling edge of the first data out clock. if the continuous read mode bits m5 - 4 = (1,0), then the next fast re ad quad i/o instruction ( after /cs is raised and then lowered) does not require the e3h instruction code, as shown in figure 1 6b. this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after /cs is asser ted low. if the continuous read mode bits m5 - 4 do not equal to (1,0), the next instruction ( after /cs is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. a continuous read mode reset instruction can also be used to reset (m7 - 0) before iss uing normal instructions (see 7 .2.20 for detail descriptions). figure 16a. octal word read quad i/o instruction sequence ( initial instruction or previous m 5 - 4 ? 10 ) m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 16 17 18 19 20 21 instruction (e3h) 4 0 5 1 6 2 7 3 byte 4
- 38 - figure 16b. octal word read quad i/o in struction sequence ( previous instruction set m5 - 4 = 10 ) m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 4 0 5 1 6 2 7 3 a15-8 a7-0 4 0 5 1 6 2 7 3 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 5 6 7 ios switch from input to output byte 3 8 9 10 11 12 13 4 0 5 1 6 2 7 3 byte 4
publication release date: january 26, 2015 - 39 - revision j 7.2.18 set burst with wrap (77h) the set burst with wrap (77h) instruction is used in conjunction with fast read quad i/o and word read quad i/o instructions to access a fixed length of 8/16/32/64 - by te section within a 256 - byte page. certain applications can benefit from this feature and improve the overall system code execution performance. similar to a quad i/o instruction, the set burst with wrap instruction is initiated by driving the /cs pin low and then shifting the instruction code 77h followed by 24 dummy bits and 8 wrap bits, w7 - 0. the instruction sequence is shown in figure 17. wrap bit w7 and the lower nibble w3 - 0 are not used. w6, w5 w4 = 0 w4 =1 (default) wrap around wrap length wrap around wrap length 0 0 yes 8 - byte no n/a 0 1 yes 16 - byte no n/a 1 0 yes 32 - byte no n/a 1 1 yes 64 - byte no n/a once w6 - 4 is set by a set burst with wrap instruction, all the following fast read quad i/o and word read quad i/o instructions wil l use the w6 - 4 setting to access the 8/16/32/64 - byte section within any page. to exit the wrap around function and return to normal read operation, another set burst with wrap instruction should be issued to set w4 = 1. the default value of w4 upon power on is 1. in the case of a system reset while w4 = 0, it is recommended that the controller issues a set burst with wrap instruction to reset w4 = 1 prior to any normal read instructions since w 25q16d v does not have a hardware reset pin. figure 17. set burst with wrap instruction sequence wrap bit /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 x x x x x x x x don't care 6 7 8 9 don't care don't care 10 11 12 13 14 15 instruction (77h) mode 0 mode 3 x x x x x x x x x x x x x x x x w4 x w5 x w6 x x x
- 40 - 7.2.19 continuous read mode bits (m7 - 0) the continuous read mode bits are used in conjunction with fast read dual i/o, fast read quad i/o, word read quad i/o and octal word read quad i/o instructions to provide the highest random flash memory access rate with minimum spi instruction overhead, thus allow true xip (execute in place) to be performed on serial flash devices. m7 - 0 need to be set by the dual/quad i/o read instructions. m5 - 4 are used to control whether the 8 - bit spi instruction code (bbh, ebh, e7h or e3h) is needed or not for the next command. when m5 - 4 = (1,0), the next command will be treated same as the current dual/quad i/o read command without needing the 8 - bit instruction code; when m5 - 4 do not equal t o (1,0), the device returns to normal spi mode, all commands can be accepted. m7 - 6 and m3 - 0 are reserved bits for future use, either 0 or 1 values can be used. 7.2.20 continuous read mode reset (ffh or ffffh) continuous read mode reset instruction can be used to set m4 = 1, thus the device will release the continuous read mode and return to normal spi operation, as shown in figure 18. figure 18. continuous read mode reset for fast read dual/quad i/o since w 25q16d v does not have a hard ware reset pin, so if the controller resets while w 25q16d v is set to continuous mode read, the w 25q16d v will not recognize any initial standard spi instructions from the controller. to address this possibility, it is recommended to issue a continuous read mode reset instruction as the first instruction after a system reset. doing so will release the device from the continuous read mode and allow standard spi instructions to be recognized. to reset continuous read mode during quad i/o operation, only eight clocks are needed. the instruction is ffh. to reset continuous read mode during dual i/o operation, sixteen clocks are needed to shift in instruction ffffh. /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 don't care 6 7 8 9 10 11 12 13 14 15 mode bit reset for quad i/o (ffh) mode 0 mode 3 mode bit reset for dual i/o (ffffh) don't care don't care
publication release date: january 26, 2015 - 41 - revision j 7.2.21 page program (02h) the page program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (ffh) memory locations. a write enable instruction must be executed before the device will accept the page program instruction (status register bit wel= 1). the instruction is initiated by driving the /cs pin low then shifting the instruction code 02h followed by a 24 - bit address (a23 - a0) and at least one data byte, into the di pin. the /cs pin must be held low for the entire length of the instruction while data is being sent to the device. the page program i nstruction sequence is shown in figure 19. if an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. if the last address byte is not zero, and the number of clocks exceed the remaining page length, the addressing will wrap to the beginning of the page. in some cases, less than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the same page. one condition to perform a partial page program is that the number of clocks can not exceed the remaining page length. if more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. as with the write and erase instructions, the /cs pin mu st be driven high after the eighth bit of the last byte has been latched. if this is not done the page program instruction will not be executed. after /cs is driven high, the self - timed page program instruction will commence for a time duration of tpp (see ac characteristics). while the page program cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is finis hed and the device is ready to accept other instructions again. after the page program cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the page program instruction will not be executed if the addressed page is pr otected by the block protect (cmp, sec, tb, bp2, bp1, and bp0) bits. figure 19. page program instruction sequence diagram /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (02h) 8 9 10 28 29 30 39 24-bit address 23 22 21 3 2 1 * /cs clk di (io 0 ) 40 41 42 43 44 45 46 47 data byte 2 48 49 50 52 53 54 55 2072 7 6 5 4 3 2 1 0 51 39 0 31 0 32 33 34 35 36 37 38 data byte 1 7 6 5 4 3 2 1 * mode 0 mode 3 data byte 3 2073 2074 2075 2076 2077 2078 2079 0 data byte 256 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 * = msb *
- 42 - 7.2.22 quad input page program ( 3 2h) the quad page program instruction allows up to 256 bytes of data to be programmed at previously erased (ffh) memory locations using four pins: io 0 , io 1 , io 2 , and io 3 . the quad page program can improve performance for prom programmer and applications that have slow clock speeds <5mhz. systems with faster clock speed will not realize much benefit for the quad page program instruction since the inherent page program time is much greater than the time it take to clock - in the data. to use quad page program the quad enable in status register - 2 must be set (qe=1). a write enable ins truction must be executed before the device will accept the quad page program instruction (status register - 1, wel=1). the instruction is initiated by driving the /cs pin low then shifting the instruction code 32h followed by a 24 - bit address (a23 - a0) and at least one data byte, into the io pins. the /cs pin must be held low for the entire length of the instruction while data is being sent to the device. all other functions of quad page program are identical to standard page program. the quad page program instruction sequence is shown in figure 20. figure 20. quad input page program instruction sequence diagram 7.2.23 sector erase (20h) the sector erase instruction sets all memory within a specified sector (4k - bytes) to the erased state of all 1s (ffh). a w rite enable instruction must be executed before the device will accept the sector erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low /cs clk mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (32h) 8 9 10 28 29 30 32 33 34 35 36 37 4 0 24-bit address 23 22 21 3 2 1 0 * 31 31 /cs clk 5 1 byte 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 byte 2 byte 3 byte 256 0 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 536 537 538 539 540 541 542 543 mode 0 mode 3 byte 253 byte 254 byte 255 io 0 io 1 io 2 io 3 io 0 io 1 io 2 io 3 * * * * * * * = msb *
publication release date: january 26, 2015 - 43 - revision j and shifting the instruction code 20h followed a 24 - bit se ctor address (a23 - a0) (see figure 2). the sector erase instruction sequence is shown in figure 21 . the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the sector erase instruction will not be executed . after /cs is driven high, the self - timed sector erase instruction will commence for a time duration of t se (see ac characteristics). while the sector erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the sector erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the sector erase cycle has finished the write enable latch (wel) bit in t he status register is cleared to 0. the sector erase instruction will not be executed if the addressed page is protected by the block protect (cmp, sec, tb, bp2, bp1, and bp0) bits (see status register memory protection table). figure 21. sector erase i nstruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (20h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
- 44 - 7.2.24 32kb block erase (52h) the block erase instruction sets all memory within a specified block (32k - bytes) to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the block erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code 52h followed a 24 - bit block address (a23 - a0) (see figure 2). the block erase instruction sequence is shown in figure 22. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase instruction will not be executed. after /cs is driven high, the self - timed block erase instruction will commence for a time duration of t be 1 (see ac characteristics). while the block erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the block erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the block erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not be executed if the addressed page is protected by the block protect (cmp, sec, tb, bp2, bp1, and bp0) bits (see status register memory protection table). figure 22. 32kb block erase instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (52h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
publication release date: january 26, 2015 - 45 - revision j 7.2.25 64kb block erase (d8h) the block erase instruction se ts all memory within a specified block (64k - bytes) to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the block erase instruction (status register bit wel must equal 1). the instruction is initiat ed by driving the /cs pin low and shifting the instruction code d8h followed a 24 - bit block address (a23 - a0) (see figure 2). the block erase instruction sequence is shown in figure 23. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase instruction will not be executed. after /cs is driven high, the self - timed block erase instruction will commence for a time duration of t be (see ac characteristics). while the block erase cycle is in p rogress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the block erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions ag ain. after the block erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not be executed if the addressed page is protected by the block protect (cmp, sec, tb, bp2, bp1, and bp0 ) bits (see status register memory protection table). figure 23. 64kb block erase instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (d8h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
- 46 - 7.2.26 chip erase (c7h / 60h ) the chip erase instruction sets all memory within the device to the erased state of all 1 s (ffh). a write enable instruction must be executed before the device will accept the chip erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code c7h or 60h . the chip erase instruction sequence is shown in figure 24. the /cs pin must be driven high after the eighth bit has been latched. if this is not done the chip erase instruction will not be executed. after /cs is driven high, the self - timed chip erase instr uction will commence for a time duration of t ce (see ac characteristics). while the chip erase cycle is in progress, the read status register instruction may still be accessed to check the status of the busy bit. the busy bit is a 1 during the chip erase c ycle and becomes a 0 when finished and the device is ready to accept other instructions again. after the chip erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the chip erase instruction will not be executed if any page is protected by the block protect (cmp, sec, tb, bp2, bp1, and bp0) bits (see status register memory protection table). figure 24. chip erase instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (c7h/60h) high impedance mode 0 mode 3
publication release date: january 26, 2015 - 47 - revision j 7.2.27 erase / program suspend (75h) the erase /pro gram suspend instruction 75h , allows the system to interrupt a s ector or b lock e rase operation or a page program operation and then read from or p rogram /erase data to, any other sector s or blocks . the erase/program suspend instruction sequence is shown i n figure 25. the write status register instruction (01h) and erase instructions (20h, 52h, d8h, c7h, 60h, 44h) are not allowed during erase suspend. erase suspend is valid only during the s ector or b lock erase operation. if written during the c hip e rase op eration, the erase suspend instruction is ignored. the write status register instruction (01h) and program instructions (02h, 32h, 42h) are not allowed during program suspend. program suspend is valid only during the page program or quad page program opera tion. the erase/program suspend instruction 75h will be accepted by the device only if the sus bit in the status register equals to 0 and the busy bit equals to 1 while a sector or block erase or a page program operation is on - going. if the sus bit equal s to 1 or the busy bit equals to 0, the suspend instruction will be ignored by the device. a maximum of time of t sus (see ac characteristics) is required to suspend the erase or program operation. the busy bit in the status register will be clear ed from 1 to 0 within t sus and the sus bit in the status register will be set from 0 to 1 immediately after erase/program suspend. for a previously resumed erase/program operation, it is also required that the suspend instruction 75h is not issued earlier than a minimum of time of t sus following the preceding resume instruction 7ah. unexpected power off during the erase/program suspend state will reset the device and release the suspend state. sus bit in the status register will also reset to 0. the data wi thin the page, sector or block that was being suspended may become corrupted. when the device is powered up again, i t is recommended for the user to repeat the same erase or program operation that was interrupted, at the same address location, to avoid the potention data corruption. figure 2 5 . erase /program suspend instruction sequence /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (75h) high impedance mode 0 mode 3 tsus accept instructions
- 48 - 7.2.28 erase / program resume (7ah) the erase /program resume instruction 7ah must be written to resume the s ector or b lock e rase operation or the p age program operation after an erase/program suspend . the resume instruction 7ah will be accepted by the device only if the sus bit in the status register equals to 1 and the busy bit equals to 0. after issued the sus bit will be clear ed from 1 to 0 imme diately, the busy bit will be set from 0 to 1 within 200ns and the sector or block will complete the erase operation or the page will complete the program operation. if the sus bit equals to 0 or the busy bit equals to 1, the resume instruction 7ah will be ignored by the device. the erase/program resume instruction sequence is shown in figure 26. resume instruction is ignored if the previous erase/program suspend operation was interrupted by unexpected power off. it is also required that a subsequent eras e/program suspend instruction not to be issued within a minimum of time of t sus following a previous resume instruction. figure 2 6 . erase /program resume instruction sequence /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (7ah) mode 0 mode 3 resume previously suspended program or erase
publication release date: january 26, 2015 - 49 - revision j 7.2.29 power - down (b9h) although the standby current dur ing normal operation is relatively low, standby current can be further reduced with the power - down instruction. the lower power consumption makes the power - down instruction especially useful for battery powered applications (see icc1 and icc2 in ac charact eristics). the instruction is initiated by driving the /cs pin low and shifting the instruction code b9h as shown in figure 2 7 . the /cs pin must be driven high after the eighth bit has been latched. if this is not done the power - down instruction will no t be executed. after /cs is driven high, the power - down state will entered within the time duration of t dp (see ac characteristics). while in the power - down state only the release from power - down / device id instruction, which restores the device to normal operation, will be recognized. all other instructions are ignored. this includes the read status register instruction, which is always available during normal operation. ignoring all but one instruction makes the power down state a useful condition for se curing maximum write protection. the device always powers - up in the normal operation with the standby current of icc1. figure 2 7 . deep power - down instruction sequence diagram /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (b9h) mode 0 mode 3 tdp power-down current stand-by current
- 50 - 7.2.30 release power - down / device id (abh) the relea se from power - down / device id instruction is a multi - purpose instruction. it can be used to release the device from the power - down state , or obtain the devices electronic identification (id) number. to release the device from the power - down state, the in struction is issued by driving the /cs pin low, shifting the instruction code abh and driving /cs high as shown in figure 2 8a . release from power - down will take the time duration of t res 1 (see ac characteristics) before the device will resume normal oper ation and other instructions are accepted. the /cs pin must remain high during the t res 1 time duration. when used only to obtain the device id while not in the power - down state, the instruction is initiated by driving the /cs pin low and shifting the instr uction code abh followed by 3 - dummy bytes. the device id bits are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 2 8a . the device id values for the w 25q16d v is listed in manufacturer and device identif ication table. the device id can be read continuously. the instruction is completed by driving /cs high. when used to release the device from the power - down state and obtain the device id, the instruction is the same as previously described, and shown in figure 2 8b , except that after /cs is driven high it must remain high for a time duration of t res 2 (see ac characteristics). after this time duration the device will resume normal operation and other instructions will be accepted. if the release from power - down / device id instruction is issued while an erase, program or write cycle is in process (when busy equals 1) the instruction is ignored and will not have any effects on the current cycle. figure 2 8a . release power - down inst ruction sequence /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (abh) mode 0 mode 3 tres1 power-down current stand-by current
publication release date: january 26, 2015 - 51 - revision j figure 2 8b . release power - down / device id instruction sequence diagram tres2 /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (abh) high impedance 8 9 29 30 31 3 dummy bytes 23 22 2 1 0 * mode 0 mode 3 7 6 5 4 3 2 1 0 * 32 33 34 35 36 37 38 device id power-down current stand-by current = msb *
- 52 - 7.2.31 read manufacturer / device id (90h) the read manufacturer/device id instruction is an alternative to the release from power - down / de vice id instruction that provides both the jedec assigned manufacturer id and the specific device id. the read manufacturer/device id instruction is very similar to the release from power - down / device id instruction. the instruction is initiated by drivi ng the /cs pin low and shifting the instruction code 90h followed by a 24 - bit address (a23 - a0) of 000000h. after which, the manufacturer id for winbond (efh) and the device id are shifted out on the falling edge of clk with most significant bit (msb) fir st as shown in figure 29 . the device id values for the w 25q16d v is listed in manufacturer and device identification table. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving /cs high. figure 29 . read manufacturer / device id diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (90h) high impedance 8 9 10 28 29 30 31 address (000000h) 23 22 21 3 2 1 0 device id * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 manufacturer id (efh) 40 41 42 44 45 46 7 6 5 4 3 2 1 0 * 43 31 0 mode 0 mode 3 = msb *
publication release date: january 26, 2015 - 53 - revision j 7.2.32 read manufacturer / device id dual i/o (92h) the manufacturer / device id dual i/o instruction is an alternative to the read manufacturer/device id instruction that p rovides both the jedec assigned manufacturer id and the specific device id at 2x speed. the read manufacturer / device id dual i/o instruction is similar to the fast read dual i/o instruction. the instruction is initiated by driving the /cs pin low and shi fting the instruction code 92h followed by a 24 - bit address (a23 - a0) of 000000h, 8 - bit continuous read mode bits, with the capability to input the address bits two bits per clock . after which, the manufacturer id for winbond (efh) and the device id are s hifted out 2 bits per clock on the falling edge of clk with most significant bits (msb) first as shown in figure 30 . the device id values for the w 25q16d v is listed in manufacturer and device identification table. the manufacturer and device ids can be rea d continuously, alternating from one to the other. the instruction is completed by driving /cs high. figure 30 . read manufacturer / device id dual i/o diagram note: the continuous read mode bits m7 - 0 must be set to fxh to be compatible with fast read dual i/o instruction. /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (92h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 7 5 3 1 * * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 23 * * a23-16 a15-8 a7-0 (00h) m7-0 /cs clk di (io 0 ) do (io 1 ) 24 25 26 27 28 29 30 31 32 33 34 36 37 38 35 23 0 mode 0 mode 3 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 6 4 2 1 0 1 mfr id device id mfr id (repeat) device id (repeat) ios switch from input to output * * * * = msb *
- 54 - 7.2.33 read manufacturer / device id quad i/o (94h) the read manufacturer / device id quad i/o instruction is an alternative to the read manufacturer / device id instruction that provides both the jedec assigned manufacturer id and the spe cific device id at 4x speed. the read manufacturer / device id quad i/o instruction is similar to the fast read quad i/o instruction. the instruction is initiated by driving the /cs pin low and shifting the instruction code 94h followed by a 24 - bit addr ess (a23 - a0) of 000000h , 8 - bit continuous read mode bits and then four clock dummy cycles, with the capability to input the address bits four bits per clock . after which, the manufacturer id for winbond (efh) and the device id are shifted out four bits per clock on the falling edge of clk with most significant bit (msb) first as shown in figure 31 . the device id values for the w 25q16d v is listed in manufacturer and device identification table. the manufacturer and device ids can be read continuously, altern ating from one to the other. the instruction is completed by driving /cs high. figure 31 . read manufacturer / device id quad i/o diagram note: the continuous read mode bits m7 - 0 must be set to fxh to be compatible with fast read quad i/o instruction. mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (94h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 5 1 4 0 23 mode 0 mode 3 ios switch from input to output high impedance 7 3 6 2 /cs clk io 0 io 1 io 2 io 3 high impedance a23-16 a15-8 a7-0 (00h) m7-0 mfr id device id dummy dummy /cs clk io 0 io 1 io 2 io 3 23 0 1 2 3 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 24 25 26 27 28 29 30 mfr id (repeat) device id (repeat) mfr id (repeat) device id (repeat)
publication release date: january 26, 2015 - 55 - revision j 7.2.34 read unique id number (4bh) the read unique id number instruction accesses a factory - set read - only 64 - bit number that is unique to each w 25q16d v device. the id number can be used in conjunction with user software methods to help prevent copying or clonin g of a system. the read unique id instruction is initiated by driving the /cs pin low and shifting the instruction code 4bh followed by a four bytes of dummy clocks. after which, the 64 - bit id is shifted out on the falling edge of clk as shown in figure 32 . figure 32 . read unique id number instruction sequence /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (4bh) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 /cs clk di (io 0 ) do (io 1 ) 24 25 26 27 28 29 30 31 32 33 34 36 37 38 35 23 mode 0 mode 3 * dummy byte 1 dummy byte 2 39 40 41 42 dummy byte 3 dummy byte 4 63 62 61 2 1 0 64-bit unique serial number 100 101 102 high impedance = msb *
- 56 - 7.2.35 read jedec id (9fh) for compatibility reasons, the w 25q16d v provides several instructions to electronically determine the identity of the device. the read jedec id instruction is compatible w ith the jedec standard for spi compatible serial memories that was adopted in 2003. the instruction is initiated by driving the /cs pin low and shifting the instruction code 9fh. the jedec assigned manufacturer id byte for winbond (efh) and two device id bytes, memory type (id15 - id8) and capacity (id7 - id0) are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 33 . for memory type and capacity values refer to manufacturer and device identification table. figure 33 . read jedec id instruction sequence /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (9fh) high impedance 8 9 10 12 13 14 15 capacity id7-0 /cs clk di (io 0 ) do (io 1 ) 16 17 18 19 20 21 22 23 manufacturer id (efh) 24 25 26 28 29 30 7 6 5 4 3 2 1 0 * 27 15 mode 0 mode 3 11 7 6 5 4 3 2 1 0 * memory type id15-8 = msb *
publication release date: january 26, 2015 - 57 - revision j 7.2.36 read sfdp register (5ah) the w 25q16d v features a 256 - byte serial flash discoverable parameter (sfdp) register that contains information about device configurations, available instruc tions and other features. the sfdp parameters updated uson 4x4 information but more may be added in the future. the read sfdp register instruction is com patible with the sfdp standard initially established in 2010 for pc and other applications, as well as the jedec standard 1.0 that is published in 2011 . most winbond spiflash memories shipped after june 2011 (date code 1124 and beyond) support the sfdp feature as specified in the applicable datasheet. the read sfdp instruction is initiated by driving the / cs pin low and shifting the instruction code 5ah followed by a 24 - bit address (a23 - a0) (1) into the di pin. eight dummy clocks are also required before the sfdp register contents are shifted out on the falling edge of the 40 th clk with most significant bit (msb) first as shown in figure 3 4 . for sfdp register values and descriptions, please refer to the winbond application note for sfdp definition table . note: 1. a23 - a8 = 0; a7 - a0 are used to define the starting byte address for the 256 - byte sfdp registe r. figure 3 4 . read sfdp register instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (5ah) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 dummy byte high impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 data out 2 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 43 31 0 = msb *
- 58 - 7.2.37 erase security registers (44h) the w 25q16d v offers three 256 - byte security registers which can be erased and programmed individually. these registers may be used by the system manufacturers to store security and other important information separately from the main memory array. the erase security register instruction is similar to the sector erase instruction. a write enable instruction must be executed before the device will accept the erase security register instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code 44h followed by a 24 - bit address (a23 - a0) to erase one of the three security registers. addr ess a23 - 16 a15 - 12 a11 - 8 a7 - 0 security register #1 00h 0 0 0 1 0 0 0 0 dont care security register #2 00h 0 0 1 0 0 0 0 0 dont care security register #3 00h 0 0 1 1 0 0 0 0 dont care the erase security register instruction sequence is shown in figu re 3 5 . the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the instruction will not be executed. after /cs is driven high, the self - timed erase security register operation will commence for a time dur ation of t se (see ac characteristics). while the erase security register cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the erase cycle and becomes a 0 wh en the cycle is finished and the device is ready to accept other instructions again. after the erase security register cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. t he security register lock bits lb [3:1] in th e status register - 2 can be used to otp protect the security registers. once a lock bit is set to 1, the corresponding security register will be permanently locked, erase security register instruction to that register will be ignored (see 7 .1.9 for detail d escriptions). figure 3 5 . erase security registers instruction sequence /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (44h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
publication release date: january 26, 2015 - 59 - revision j 7.2.38 program security registers (42h) the program security register instruction is similar to the page program instruction. it allows from one byte to 256 bytes of security register data to be programmed at previously erased (ffh) memory locations. a write enable instruction must be executed before the device will accept the program security register instruction (status register bit wel= 1). the instruction is initiated by driving the /cs pin low then shifting the instruction code 42h followed by a 24 - bit address (a23 - a0) and at least one data byte, into the di pin. the /cs pin must be held low for the entire length of the instruction while data is being sent to the device. address a23 - 16 a15 - 12 a11 - 8 a7 - 0 security register #1 00h 0 0 0 1 0 0 0 0 byte address security register #2 00h 0 0 1 0 0 0 0 0 byte address security register #3 00h 0 0 1 1 0 0 0 0 byte address the program security register instruction sequence is shown in figur e 3 6 . the se curity register lock bits lb[3:1] in the status register - 2 can be used to otp protect the security registers. once a lock bit is set to 1, the corresponding security register will be permanently locked, program security register instruction to that register will be ignored (see 7 .1.9, 7 .2.21 for detail descriptions). figure 3 6 . program security registers instruction sequence /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (42h) 8 9 10 28 29 30 39 24-bit address 23 22 21 3 2 1 * /cs clk di (io 0 ) 40 41 42 43 44 45 46 47 data byte 2 48 49 50 52 53 54 55 2072 7 6 5 4 3 2 1 0 51 39 0 31 0 32 33 34 35 36 37 38 data byte 1 7 6 5 4 3 2 1 * mode 0 mode 3 data byte 3 2073 2074 2075 2076 2077 2078 2079 0 data byte 256 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 * = msb *
- 60 - 7.2.39 read security registers (48h) the read security register instruction is similar to the fast read instruction and allo ws one or more data bytes to be sequentially read from o ne of the three security registers. the instruction is initiated by driving the /cs pin low and then shifting the instruction code 48h followed by a 24 - bit address (a23 - a0) and eight dummy clocks into the di pin. the code and address bits are latched on the rising edge of the clk pin. after the address is received, the data byte of the addressed memory location will be shifted out on the do pin at the falling edge of clk with most significant bit (msb) first. the byte address is automatically incremented to the next byte address after each byte of data is shifted out. once the byte address reaches the last byte of the register (byte ffh), it will reset to 00h, the first byte of the register, and co ntinue to increment. the instruction is completed by driving /cs high. the read security register instruction sequence is shown in figure 3 7 . if a read security register instruction is issued while an erase, program or write cycle is in process (busy=1) th e instruction is ignored and will not have any effects on the current cycle. the read security register instruction allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). address a23 - 16 a15 - 12 a11 - 8 a7 - 0 security register #1 00h 0 0 0 1 0 0 0 0 byte address security register #2 00h 0 0 1 0 0 0 0 0 byte address security register #3 00h 0 0 1 1 0 0 0 0 byte address figure 3 7 . read security registers instruction sequence /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (48h) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 dummy byte high impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 data out 2 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 43 31 0 = msb *
publication release date: january 26, 2015 - 61 - revision j 7.2.40 enable reset (66h) and reset (99h) because of th e small package and the limitation on the number of pins, the w25q16dv provide a software reset instruction instead of a dedicated reset pin. once the reset instruction is accepted, any on - going internal operations will be terminated and the device will re turn to its default power - on state and lose all the current volatile settings, such as volatile status register bits, write enable latch (wel) status, program/erase suspend status, read parameter setting (p7 - p0), continuous read mode bit setting (m7 - m0) an d wrap bit setting (w6 - w4). enable reset (66h) and reset (99h) instructions must be issued in sequence to avoid accidental reset. any other commands other than reset (99h) after the enable reset (66h) command will disable the reset enable state. a new sequence of enable reset (66h) and reset (99h) is needed to reset the device. once the reset command is accepted by the device, the device will take approximately trst=30us to reset. during this period, no command will be accepted. data corruptio n may happen if there is an on - going or suspended internal erase or program operation when reset command sequence is accepted by the device. it is recommended to check the busy bit and the sus bit in status register before issuing the reset command sequenc e. figure 38 . enable reset and reset instruction sequence mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (99h) mode 0 mode 3 /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (66h) high impedance
- 62 - 8. electrical character istics 8.1 absolute maximum ratings ( 1 ) parameters symbol conditions range unit supply voltage vcc C 0.6 to +4. 6 v voltage applied to any pin v io rela tive to ground C 0.6 to vcc +0.4 v transient voltage on any pin v iot <20ns transient relative to ground C 2.0v to vcc+2.0v v storage temperature t stg C 65 to +150 c lead temperature t lead see note ( 2 ) c electrostatic discharge voltage v esd human body m odel ( 3 ) C 2000 to +2000 v notes: 1 . this device has been designed and tested for the specified operation ranges. proper operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may affect device reliability. exposure beyon d absolute maximum ratings may cause permanent damage. 2 . compliant with jedec standard j - std - 20c for small body sn - pb or pb - free (green) assembly and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. 3 . jedec std jesd22 - a11 4a (c1=100pf, r1=1500 ohms, r2=500 ohms). 8.2 operating ranges parameter symbol conditions spec unit min max supply voltage vcc f r = 8 0mhz, f r = 50 mhz f r = 104 mhz, f r = 50 mhz 2.7 3.0 3. 0 3.6 v ambient temperature, operating t a industrial - 40 +85 c
publication release date: january 26, 2015 - 63 - revision j 8.3 power - u p power - down timing and requirements parameter symbol spec unit min max vcc (min) to /cs low t vsl (1) 2 0 s time delay before write instruction t puw (1) 5 ms write inhibit threshold voltage v wi (1) 1.0 2.0 v note: 1. these parame ters are characterized only. figure 39a . power - up timing and voltage levels figure 39b. power - up, power - down requirement vcc tvsl read instructions allowed device is fully accessible tpuw /cs must track vcc program, erase and write instructions are ignored reset state vcc (max) vcc (min) v wi time vcc time / cs must track vcc during vcc ramp up / down / cs
- 64 - 8.4 dc electrical characteristics parameter symbol conditions spec unit mi n typ max input capacitance c in (1) v in = 0v (1) 6 pf output capacitance cout (1) v out = 0v (1) 8 pf input leakage i li 2 a i/o leakage i lo 2 a standby current i cc 1 /cs = vcc, vin = gnd or vcc 10 50 a power - down current i cc 2 /cs = vc c, vin = gnd or vcc 1 5 a current read data normal read 50mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 8 10 ma current read data / dual output read /quad output read 80mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 1 2 1 8 ma current write status regi ster i cc 4 /cs = vcc 20 25 ma current page program i cc 5 /cs = vcc 20 25 ma current sector/block erase i cc 6 /cs = vcc 20 25 ma current chip erase i cc 7 /cs = vcc 20 25 ma input low voltage v il vcc x 0.3 v input high voltage v ih vcc x 0.7 v output low voltage v ol i ol = 100 a 0.2 v output high voltage v oh i oh = C 100 a vcc C 0.2 v notes: 1 . tested on sample basis and specified through design and characterization data. ta = 25 c, vcc = 3 v. 2 . checker board pattern.
publication release date: january 26, 2015 - 65 - revision j 8.5 ac measurement c onditions parameter symbol spec unit min max load capacitance c l 30 pf input rise and fall times t r , t f 5 ns input pulse voltages v in 0. 1 vcc to 0. 9 vcc v input timing reference voltages in 0.3 vcc to 0.7 vcc v output timing reference voltage s o ut 0. 5 vcc to 0. 5 vcc v note: 1. output hi - z is defined as the point where data out is no longer driven. figure 40 . ac measurement i/o waveform input and output timing reference levels input levels 0.9 vcc 0.1 vcc 0.5 vcc
- 66 - 8.6 ac electrical characteristics description symbol alt spec unit min typ max clock frequency for all instructions, except read data (03h) 2.7 - 3.0 v / 3.0 - 3.6v & industrial temperature f r f c d.c. 80 /104 mhz clock freq. read data instruction ( 03h ) f r d.c. 50 mhz clock high, low time except read data (03h) t clh , t cll ( 1) 4 ns clock high, low time for read data (03h) instruction t crlh , t crll ( 1) 8 ns clock rise time peak to peak t clch ( 2) 0.1 v/ns clock fall time peak to peak t chcl ( 2) 0.1 v/ns /cs active setup time relative to clk t slch t css 3 ns /cs not a ctive hold time relative to clk t chsl 3 ns data in setup time t dvch t dsu 2 ns data in hold time t chdx t dh 3 ns /cs active hold time relative to clk t chsh 3 ns /cs not active setup time relative to clk t shch 3 ns /cs deselect time (for a rray read ? array read) t shsl 1 t csh 10 ns /cs deselect time (for erase/ program ? read sr) volatile status register write time t shsl 2 t csh 50 50 ns output disable time t shqz ( 2) t dis 7 ns clock low to output valid 2.7 - 3.0v / 3.0 - 3.6v t clqv 1 t v 1 7 / 6 ns clock low to output valid (for read id instructions) 2.7 - 3.0 v / 3.0 - 3.6v t clqv 2 t v 2 8.5 / 7.5 ns output hold time t clqx t ho 0 ns /hold active setup time relative to clk t hlch 3 ns continued C next page
publication release date: january 26, 2015 - 67 - revision j 8.7 ac electrical characteristics ( contd) description symbol alt spec unit min typ max /hold active hold time relative to clk t chhh 3 ns /hold not active setup time relative to clk t hhch 3 ns /hold not active hold time relative to clk t chhl 3 ns /hold to output low - z t hh qx ( 2) t lz 7 ns /hold to output high - z t hlqz ( 2) t hz 12 ns write protect setup time before /cs low t whsl ( 3) 20 ns write protect hold time after /cs high t shwl ( 3) 100 ns /cs high to power - down mode t dp ( 2) 3 s /cs high to standby mode witho ut electronic signature read t res 1 ( 2) 3 s /cs high to standby mode with electronic signature read t res 2 ( 2) 1.8 s /cs high to next instruction after suspend t sus ( 2) 20 s write status register time t w 1 0 15 ms byte program time (first byte ) (4 ) t bp1 2 0 50 s additional byte program time (after first byte) (4 ) t bp2 2.5 1 0 s page program time t pp 0.7 3 ms sector erase time (4kb) t se 6 0 200 /400 (5) ms block erase time ( 32 kb) t be 1 1 5 0 8 00 ms block erase time (64kb) t be 2 1 8 0 1 , 000 ms chip erase time t ce 3 10 s notes: 1. clock high + clock low must be less than or equal to 1/f c . 2. val ue guaranteed by design and/or characterization, not 100% tested in production. 3. only applicable as a constraint for a write status register instruc tion when srp [1:0]=( 0 ,1) . 4. for multiple bytes after first byte within a page, t bpn = t bp1 + t bp2 * n (typical) and t bpn = t bp1 + t bp2 * n (max), where n = number of bytes programmed . 5. max value tse with <50k cycles is 200ms and >50k & <100k cycles is 400ms.
- 68 - 8.8 serial output timing 8.9 serial input timing 8.10 /hold timing 8.11 /wp timing /cs clk io output tclqx tclqv tclqx tclqv tshqz tcll lsb out tclh msb out /cs clk io input tchsl msb in tslch tdvch tchdx tshch tchsh tclch tchcl lsb in tshsl /cs clk io output /hold tchhl thlch tchhh thhch thlqz thhqx io input /cs clk /wp twhsl tshwl io input write status register is allowed write status register is not allowed
publication release date: january 26, 2015 - 69 - revision j 9. package specificatio n 9.1 8 - pin soic 150 - mil (package code sn) symbol mil limeters inches min max min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.008 0.010 e (3) 3.80 4.00 0.150 0.157 d (3) 4.80 5.00 0.188 0.196 e (2) 1.27 bsc 0.050 bsc h e 5.80 6.20 0.228 0.244 y (4) --- 0.10 --- 0.004 l 0.40 1.27 0.016 0.050 0 10 0 10 notes: 1. controlling dimensions: millimeters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash protrusions and should be meas ured from the bottom of the package. 4. formed leads coplanarity with respect to seating plane shall be within 0.004 inches. l c d a1 a e b seating plane y 0.25 gauge plane e h e 4 1 5 8 l c d a1 a e b b b seating plane y 0.25 gauge plane e h e e h e 4 1 5 8
- 70 - 9.2 8 - pin soic 208 - mil (package code ss) symbol millimeters inches min nom max min nom max a 1.75 1.95 2.16 0.069 0.077 0.085 a1 0.05 0.15 0.25 0.002 0.006 0.010 a2 1.70 1.80 1.91 0.067 0.071 0.075 b 0.35 0.42 0.48 0.014 0.017 0.019 c 0.19 0.20 0.25 0.007 0.008 0.010 d 5.18 5.28 5.38 0.204 0.208 0.212 d1 5.13 5.23 5.33 0.202 0.206 0.210 e 5.18 5.28 5.38 0.204 0.208 0.212 e 1 5.13 5.23 5.33 0.202 0.206 0.210 e (2) 1.27 bsc . 0.050 bsc . h 7.70 7.90 8.10 0.303 0.311 0.319 l 0.50 0.65 0.80 0.020 0.026 0.031 y --- --- 0.10 --- --- 0.004 0 --- 8 0 --- 8 notes: 1. controlling dimensions: milli meters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d1 and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads coplanarity with respect to seating plane shall be within 0.004 inches. gauge plane gauge plane
publication release date: january 26, 2015 - 71 - revision j 9.3 8 - pin pdip 300 - mil (package code da) symbo l millimeters inches min nom max min nom max a --- --- 5.33 --- --- 0.210 a1 0.38 --- --- 0.015 --- --- a2 3.18 3.30 3.43 0.125 0.130 0.135 d 9.02 9.27 10.16 0.355 0.365 0.4 00 e 7.62 bsc. 0.300 bsc. e1 6.22 6.35 6.48 0.245 0.250 0.255 l 2.92 3.30 3.81 0.115 0.130 0.150 e b 8.51 9.02 9.53 0.335 0.355 0.375 0 7 15 0 7 15
- 72 - 9.4 8 - pad wson 6x5mm (package code zp) symbol millimeters inches min nom max min nom max a 0.70 0.75 0.80 0.02 8 0.0 30 0.031 a1 0.00 0.02 0.05 0.000 0.00 1 0.00 2 b 0.35 0.40 0.48 0.01 4 0.01 6 0.01 9 c --- 0.20 ref. --- --- 0.008 ref. --- d 5.90 6.00 6.10 0.232 0.236 0.240 d2 3.35 3.40 3.45 0.13 2 0.13 4 0.13 6 e 4.90 5.00 5.10 0.19 3 0.19 7 0.2 0 1 e2 4.25 4.30 4.35 0.167 0.169 0.171 e (2) 1.27 bsc . 0.050 bsc . l 0.55 0.60 0.65 0.02 2 0.02 4 0.02 6 y 0.00 --- 0.075 0.000 --- 0.00 3 notes: 1. advanced packaging information; please contact winbond for the latest minimum and maximum specifications . 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash protrusions and should be measured from the bottom of the package. 4. the metal pad area on the bottom center of the package is connected to the device ground (g nd pin). avoid placement of exposed pcb vias under the pad.
publication release date: january 26, 2015 - 73 - revision j 9.5 8 - pad uson 4x3 - mm (package cod e uu) symbol millimeters inches min nom max min nom max a 0.50 0.55 0.60 0.020 0.022 0.024 a1 0.00 0.02 0.05 0.000 0. 001 0.002 a3 --- 0.15 --- --- 0.006 --- b 0.25 0.30 0.35 0.010 0.012 0.014 d 3.90 4.00 4.10 0.153 0.157 0.161 d1 0.70 0.80 0.90 0.027 0.031 0.035 d2 0.70 0.80 0.90 0.027 0.031 0.035 e 2.90 3.00 3.10 0.114 0.118 0.122 e1 0.10 0.20 0.30 0.004 0.008 0. 012 e 0.80 bsc 0.031 bsc l 0.55 0.60 0.65 0.022 0.024 0.026 note: the metal pad area on the bottom center of the package is not connected to any internal electrical signals. it can be left floating or connected to t he device ground (gnd pin). avoid pla cement of exposed pcb vias under the pad .
- 74 - 9.6 8 - pad uson 4x4 - mm (package cod e uz) symbol millimeters min nom max a 0.50 0.55 0.60 a1 0.00 0.02 0.05 b 0.25 0.30 0.35 c --- 0.15ref --- d 3.90 4.00 4.10 d2 2.95 3.00 3.05 e 3.90 4.00 4.10 e2 2.25 2.30 2.35 e --- 0.80 --- l 0.35 0.40 0.45 y 0.00 --- 0.075 note: the metal pad area on the bottom center of the package is not connected to any internal electrical signals. it can be left floating or connected to t he device ground (gnd pin). avoid pl acement of exposed pcb vias under the pad . 9.7 16 - pin soic 300 - mil (package code sf)
publication release date: january 26, 2015 - 75 - revision j symbol millimeters inches min nom max min nom max a 2.36 2.49 2.64 0.093 0.098 0.104 a1 0.10 --- 0.30 0.004 --- 0.012 a 2 --- 2.31 --- --- 0.091 --- b 0.33 0.41 0.51 0.013 0.016 0.020 c 0.18 0.23 0.28 0.007 0.009 0.011 d 10.08 10.31 10.49 0.397 0.406 0.413 e 10.01 10.31 10.64 0.394 0.406 0.419 e 1 7.39 7.49 7.59 0.291 0.295 0.299 e (2) 1.27 bsc . 0.050 bsc . l 0. 38 0.81 1.27 0.015 0.032 0.050 y --- --- 0.076 --- -- - 0.003 0 --- 8 0 --- 8 notes: 1. controlling dimensions: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. gauge plane detail a gauge plane detail a
- 76 - 9.8 24 - ball tfbga 8x6 - m m (package cod e tb, 5x5 - 1 ball array ) symbol millimeters inches min nom max min nom max a --- --- 1.20 --- --- 0.047 a1 0.25 0.30 0.35 0.01 0 0.0 12 0.0 14 a2 --- 0.85 --- --- 0.033 --- b 0.35 0.40 0.45 0.01 4 0.0 16 0.0 18 d 7.90 8.00 8.10 0 .311 0.31 5 0.31 9 d 1 4.00 bsc 0.157 bsc e 5.90 6.00 6.10 0.232 0.236 0.240 e 1 4.00 bsc 0.157 bsc se 1.00 typ 0.039 typ sd 1.00 typ 0.039 typ e 1.00 bsc 0.039 bsc 9.9 24 - ball tfbga 8x6 - m m (package cod e tc , 6x4 ball arra y ) note: ball land: 0.45mm. ball opening: 0.35mm pcb ball land suggested <= 0.35mm
publication release date: january 26, 2015 - 77 - revision j symbol millimeters inches min nom max min nom max a --- --- 1.20 --- --- 0.047 a1 0.25 0.30 0.35 0.01 0 0.0 12 0.0 14 b 0.35 0.40 0.45 0.014 0.0 16 0.0 18 d 7.95 8.00 8.05 0 .313 0.3 1 5 0.31 7 d 1 5.00 bsc 0.197 bsc e 5.95 6.00 6.05 0.234 0.236 0.238 e 1 3.00 bsc 0.118 bsc e 1.00 bsc 0.039 bsc
- 78 - 10. ordering information notes: 1. t he w prefix is not included on the part marking. 2. only the 2 nd letter is used for the part marking; wson package type zp is not used for the part marking. 3. standard bulk shipments are in tube (shape e). please specify alternate packing method, such as tape and reel (sh a pe t) or tray (shape s) , when placing orders. 4. for special option q devices, qe bit may be r eset to 0 if write status register command is only followed by 8 - bit data (status register - 1). 5. for shipments with otp feature enabled devices (p), please contact winbond w ( 1 ) 25q 16d v xx ( 2 ) w = winbond 25 q = s pi flash serial flash memory with 4 kb sectors, dual /quad i/o 16d = 1 6m - bit v = 2.7v to 3.6v ( 4,5 ) g = green package (lead - free, rohs compliant, halogen - free (tbba), antimony - oxide - free sb 2 o 3 ) q = green package with qe=1 in status register - 2 s n = soic - 8 150 - mil zp = wson - 8 6x5 - mm uu = 8 - pad uson 4x3mm uz = 8 - pad uson 4x4mm ss = soic - 8 208 - mil da = pdip - 8 300 - mil sf = 16 - pin soic 300 - mil tb = 5x5 - 1 balls tfbga 8x6 - mm tc = 6x4 balls tfbga 8x6 - mm i = industrial ( - 40 c to +85c)
publication release date: january 26, 2015 - 79 - revision j 10.1 valid pa rt numbers and top side marking the following table provides the valid part n umbers for the w 25q16d v spiflash memory . please contact winbond for specific availability by density and package type. winbond spiflash memories use an 1 2 - digit product number for ordering. however, due to limited space, the top side marking on all package s use an abbreviated 10 - digit number. package type density product number top side marking sn (2) soic - 8 150mil 16m - bit w 25q16d vsnig 25q16d vnig ss soic - 8 208mil 16m - bit w 25q16d vssig w 25q16d vssi q 25q16d vs ig 25q16d vsi q sf soic - 16 300 - mil 16m - bit w 25q16d vs f ig 25q16d v f ig zp ( 1 ) wson - 8 6x5mm 16m - bit w 25q16d vzpig w 25q16d vzpi q 25q16d vig 25q16d vi q da pdip - 8 300mil 16m - bit w 25q16d vdaig w 2 5q16d vdai q 25q16d vaig 25q16d vai q uu uson - 8 4x3mm 16m - bit w25q16 dv uuig q16 dv u u ig u z uson - 8 4x4 mm 16m - bit w25q16 dv u z ig q16 dv u z ig tb (2) tfbga - 24 8x6mm 5x5 ball array 16m - bit w 25q16d vtbig 25q16d vbig tc (2) tfbga - 24 8x6mm 6x4 ball array 16m - bit w 25q16d vtcig 25q16d vcig notes: 1. wson package type zp is not used in the top side marking. 2. these package types are special order o nly, please contact winbond for more information.
- 80 - 11. revision hi story version date page description a 0 3 / 22 /1 2 new create preliminary b 0 7 / 30 /12 all 10, 13, 63 removed qpi functions updated power down requirement c 10/ 02 /12 63 64 updated power - up timing parameters updated icc4 d 1 0 /2 9 /12 all 64, 66, 67 80 removed preliminary designator updated icc1 - 4, setup/hold time, tw, tbe updated valid part numbers e 11/29/12 64 80 updated icc1 updated valid part numbers f 10/15/13 79 5,79 updated otp enable feature, pls contact winbond removed non - available vsop package g 0 5/23 / 14 5 - 6,74,78 - 79 52 - 54 73 added uson 4x3 package modified the description of 90h/92h/94h removed unaviable package information h 10/06/14 77 - 78 updated w25q16dvsfig information i 11/18/14 74,78 - 79 updated uson 4x4mm information j 01/26/15 79 updated uson 4x4mm part no. information trademarks winbond and s piflash are trademarks of winbond electronics corporation . all other marks are the property of their respective owner. important notice winbond products are not designed, intended, authorized or war ranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for ot her applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmenta l damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. information in this document is pr ovided solely in connection with winbond products. winbond reserves the right to make changes, corrections, modifications or improvements to this document and the products and services described herein at any time, without notice.

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